Abstract: A register not connected to a data bus is read by transferring data across an address bus to a device connected to the data bus, from which the data is read by a device connected to the data bus. The register resides in a register device connected via the address bus to a memory device that is connected to both the address bus and the data bus. A host processor triggers the register device to transfer information over the address bus to a register on the memory device. The host processor then reads the information from the register of the memory device.

Abstract: A method, system and apparatus to self-determine equalization parameters for a channel. An initiator sends an equalization insensitive signal (EIS) to a responder on channel to be equalized and begins a count. A responder responds with an EIS. When the initiator receives the response EIS the count is terminated. The count, which constitutes a measure of delay in the channel, may be used to determine desirable equalization parameters for the channel.

Abstract: Link initialization techniques to decouple the read training from the write training. Read training may be accomplished in a robust manner before write training is performed. These techniques may provide significantly improved link initialization times. A user-programmable register within a dynamic random access memory (DRAM) module may be utilized by the decoupled read training and write training processes. The decoupling may result in shorter and more robust training segments that may support faster training and/or increased link speeds.

Abstract: Link initialization techniques to decouple the read training from the write training. Read training may be accomplished in a robust manner before write training is performed. These techniques may provide significantly improved link initialization times. A user-programmable register within a dynamic random access memory (DRAM) module may be utilized by the decoupled read training and write training processes. The decoupling may result in shorter and more robust training segments that may support faster training and/or increased link speeds.

Abstract: A method includes detecting a change in temperature in an integrated circuit that is coupled to a differential communication link, and responding to the detected change in temperature by initiating a retraining process for the differential communication link.

Abstract: A method includes detecting a change in temperature in an integrated circuit that is coupled to a differential communication link, and responding to the detected change in temperature by initiating a retraining process for the differential communication link.

Abstract: A method for optimizing a source synchronous clock reference signal timing to capture data from a memory device (e.g., DDR SDRAM) includes conducting an iterative two-dimensional data eye search for optimizing the delay of the source synchronous clock reference signal (e.g., DQS). Embodiments of the present invention are directed to tuning the delay for each device for the optimal margin in two dimensions: maximize the distance from the data eye walls and maximize the noise margin on the interface. An iterative data eye search is performed while varying the DQS delay timing and noise margin.

Abstract: A method, system and apparatus to self-determine equalization parameters for a channel. An initiator sends an equalization insensitive signal (EIS) to a responder on channel to be equalized and begins a count. A responder responds with an EIS. When the initiator receives the response EIS the count is terminated. The count, which constitutes a measure of delay in the channel, may be used to determine desirable equalization parameters for the channel.

Abstract: A method for optimizing a source synchronous clock reference signal timing to capture data from a memory device (e.g., DDR SDRAM) includes conducting an iterative two-dimensional data eye search for optimizing the delay of the source synchronous clock reference signal (e.g., DQS). Embodiments of the present invention are directed to tuning the delay for each device for the optimal margin in two dimensions: maximize the distance from the data eye walls and maximize the noise margin on the interface. An iterative data eye search is performed while varying the DQS delay timing and noise margin.

Abstract: A method of controlling a slew rate includes applying a resistive load to a bus corresponding to the number of logic components in a computer. The number of logic components within the computer is varied by either adding or removing a logic component. A second resistive load is selected to be applied to the bus after the number of logic circuits in the computer has been changed. The selection of a second resistance enables the slew rate to be controlled when the number of components change.

Abstract: A slew rate control circuit of a bus includes two connection devices that are adapted to be coupled to two voltage supplies. The connection devices are connected to the bus by a select terminal of a signal application device. The signal application device has first and second positions which apply first and second amounts of resistance to the bus depending on the voltage on the select terminal. If an expansion board is adapted to be coupled to the bus, a different voltage is applied on the select terminal. A method for controlling a slew rate includes applying a resistive load to a bus corresponding to the number of logic circuits in a computer system. The number of logic circuits within the computer is varied by either adding or removing a logic circuit. A second resistive load is selected to be applied to the bus after the number of logic circuits in the computer system has been varied. The selection of a second resistance enables the amount of slew rate to be reduced.

Abstract: A method for processing chlorosilane distillation residues by hydrolysis with steam, in which the hydrolysis is carried out at escalating temperatures from about 130.degree. C. to at least 170.degree. C.

Abstract: A process for waste liquid-free processing of residues of chlorosilane distillations, wherein the residue is allowed to react with liquid hydrochloric acid accompanied by the release of hydrogen chloride, the resulting reaction mixture is allowed to coagulate, the solid phase is separated and dried and heat-treated, and the liquid phase and the condensed gaseous constituents are recycled into the process.

Abstract: A residue from the production of chlorosilanes from raw silicon is treated with steam and aditionally with nitrogen-oxygen mixtures. The resulting residue has a lower chloride content.

Abstract: Residues which are obtained from the distillation of chlorosilanes prepared by reaction of raw silicon with chlorine or hydrogen chloride are processed by treatment in aqueous phase with an excess of at least 15% of calcium carbonate, and the liquid components are recycled into the process so that no liquid waste is formed.

Abstract: Disclosed is a method for the processing of the residues that occur in the production of chlorosilane. The processing is performed by the separation of the residual chlorosilanes, followed by hydrolysis of these residues with water vapor. The water vapor used has a temperature between 100.degree. and 300.degree. C. and additionally contains hydrogen chloride. The hydrolysis residues occurring in the present method have an extremely small chloride content and can be transported, if desired, directly to a dump. The hydrogen chloride that is released can be absorbed in water and removed as hydrochloric acid or can be desorbed for further technical use. Preferably it is reused for chlorosilane production.

Abstract: A method for increasing the trichlorosilane yield in the hydrochlorination of silicon in a fluidized bed involves chilling the gas mixture issuing from the fluidized bed in the shortest possible time immediately after leaving the fluidized bed to temperatures below 550.degree. C. When the temperature of the fluidized bed is below 550.degree. C., the gas mixture is chilled to temperature 100.degree. C. lower than the reaction temperature in the fluidized bed. The method makes it possible, at a reaction temperature of, for example, 800.degree. C. to increase the 16 to 20% trichlorosilane yields obtained formerly at this temperature to 55%, especially when gaseous silicon tetrachloride is also added to the fluidized bed.

Abstract: A process is described for increasing the percentage of silicon tetrachloride during the reaction of hydrogen chloride or a mixture of hydrogen chloride and chlorine with substances containing metallic silicon. In this process the chlorosilanes are exposed to a temperature ranging between 300.degree. C. and 1400.degree. C.

Abstract: Disclosed is a process for the cleavage of chlorosiloxanes in the gas phase at temperatures between 350 and 1450.degree. C. to form chlorosilanes and silicon dioxide as reaction products. The claimed process is preferably performed in the presence of metallic silicon or ferrosilicon. The procedure can be combined with the large-scale technical production of chlorosilanes by the chlorination or hydrochlorination of silicon. The inventive process makes it possible to perform the chlorination or hydrochlorination of silicon with the formation of chlorosilanes in an increased yield while reducing the formation of by-products.