Abstract: A computer-readable medium embodies a computer program for obtaining information for a payment transaction. The computer program comprises computer-readable program code for: generating a first message including an identifier and a request for the information, sending the first message via a first communication path, receiving a second message including the information and the identifier via a second path different from the first communication path, and processing the payment transaction using the information obtained in the second message.

Abstract: A computer-readable medium embodies a computer program for obtaining information for a payment transaction. The computer program comprises computer-readable program code for: generating a first message including an identifier and a request for the information, sending the first message via a first communication path, receiving a second message including the information and the identifier via a second path different from the first communication path, and processing the payment transaction using the information obtained in the second message.

Abstract: A computer-readable medium embodies a computer program for authenticating a user. The computer program comprises computer-readable program code for: generating a first message including an identifier for a session, sending the first message through an interface associated with the session, receiving a response message including the identifier for the session, a user identifier, and at least a portion encrypted using a private key associated with a mobile device associated with the user, and authenticating the user in response to identifying that the response message includes at least the portion encrypted using the private key associated with the mobile device.

Abstract: A computer-readable medium embodies a computer program for registering a mobile device. The computer program comprises computer-readable program code for: generating a first message including a first code in response to receiving a request to register the mobile device for use with a future session with an entity, sending the first message including the first code, receiving a second message including the first code and at least a portion encrypted using a private key associated with the mobile device, and registering the mobile device for use with the future session based on at least the portion of the second message being encrypted using the private key associated with the mobile device.

Abstract: A computer-readable medium embodies a computer program for registering a mobile device. The computer program comprises computer-readable program code for: generating a first message including a first code in response to receiving a request to register the mobile device for use with a future session with an entity, sending the first message including the first code, receiving a second message including the first code and at least a portion encrypted using a private key associated with the mobile device, and registering the mobile device for use with the future session based on at least the portion of the second message being encrypted using the private key associated with the mobile device.

Abstract: A computer-readable medium embodies a computer program for authenticating a user. The computer program comprises computer-readable program code for: generating a first message including an identifier for a session, sending the first message through an interface associated with the session, receiving a response message including the identifier for the session, a user identifier, and at least a portion encrypted using a private key associated with a mobile device associated with the user, and authenticating the user in response to identifying that the response message includes at least the portion encrypted using the private key associated with the mobile device.

Abstract: A computer-readable medium embodies a computer program for obtaining information for a payment transaction. The computer program comprises computer-readable program code for: generating a first message including an identifier and a request for the information, sending the first message via a first communication path, receiving a second message including the information and the identifier via a second path different from the first communication path, and processing the payment transaction using the information obtained in the second message.

Abstract: In one aspect of the invention, a method for datagram staggering in a communication system includes receiving samples of a first input signal and a second input signal. The first input signal corresponds to a first communication device, and the second input signal corresponds to a second communication device. The method also includes generating a first plurality of datagrams containing at least a portion of the samples of the first input signal. In addition, the method includes generating a second datagram containing at least a portion of the samples of the second input signal. The second datagram is staggered from each of the first plurality of datagrams such that the second datagram is ready for communication at a different time than any of the first plurality of datagrams.

Abstract: A transmission circuit for transmitting data from a host to a remote includes a plurality of memory queues, and a memory controller operable to prefetch a burst of data cells from the host, wherein a first data cell of the burst is transmitted by the memory controller to the remote and the remainder of the data cells of the burst are stored in the plurality of memory queues for later transmission to the remote.

Abstract: A method of scheduling transmission of a plurality of cells of a first signal packet associated with a first virtual channel address using a scheduling ring having a plurality of slots and pointer operable to indicate a current slot includes advancing the pointer to a slot associated with the first virtual channel address, initiating transmission of a previously scheduled first cell associated with the first virtual channel address, rescheduling transmission of a previously unscheduled second cell associated with the first virtual channel address for transmission at a later time, and advancing the pointer to the next slot.

Abstract: A system and method for controlling data flow in an available bit rate asynchronous transfer mode ATM network. In the ATM network, a transmitting end station transmits data to a receiving end station across the network. The transmitting end station sends forward resource management (RM) cells across the network, while the receiving end station sends solicited or unsolicited backward RM cells across the network. The receiving end station contains a control module that generates and transmits an unsolicited RM cell having a desired low data flow rate to transmitting end station upon detecting congestion at the receiving end station. The control module also generates and transmits an unsolicited RM cell having a desired high data flow rate to the transmitting end station upon detecting absence of congestion at the receiving end station.

Abstract: A data transmission system includes a memory, a remote coupled to the memory by a receive data controller, and a host coupled to the memory by a transmit data controller. The system prioritizes the transmission of data cells from the remote to the host based on demand by dynamically allocating portions of the memory to data cells sharing a common and frequently recurring address at the host, and transmitting to the host incihvidual data cells together in a burst.

Abstract: A modem operable to facilitate communication between a host and a communications link includes a memory operable to store a rate control algorithm. The modem further comprises a controller operable to receive from the universal serial bus a first USB segment comprising a first plurality of ATM cells and rate control information associated with the first plurality of ATM cells, to store the first plurality of ATM cells in the memory, to perform the rate control algorithm on the first plurality of ATM cells using the rate control information received in the first USB segment, and to transmit each of the plurality of ATM cells at a particular transmission rate according to the results of the rate control algorithm.

Abstract: An ATM adapter for desktop applications includes an adapter for interfacing an ATM network. The adapter includes an ATM application specific integrated circuit (ASIC). The ATM ASIC may interface with a data bus such as an SBus using a host interface circuit. The host interface circuit includes a bus interface, a DMA controller and a slave access controller. The DMA controller controls DMA operations within the ATM ASIC and associates with a RAM interface arbiter. The slave access controller controls operation of an interrupt circuit that goes to the SBus as well as a statistics circuit. The RAM interface arbiter arbitrates communication between the DMA controller, the slave access control circuit, a segmentation engine, and a reassembly engine. The RAM interface arbiter communicates with the RAM bus to a RAM associated with an adapter. The segmentation engine segments data into ATM format for transfer through a physical interface circuit.

Abstract: A multiple mode xDSL interface (60) is disclosed. The multiple mode xDSL interface (60) includes an xDSL termination unit (62) operable to couple to an XDSL link (64) and to manage communication of data across an xDSL physical layer. The mulitple mode xDSL interface (60) also includes a customer premises equipment (CPE) termination unit (65) coupled to the xDSL termination unit (62) and operable to couple to customer premises equipment. The CPE termination unit (65) has an operating mode selected from a plurality of operating modes where each operating mode is associated with a data protocol and supports communication of data across the xDSL physical layer using the associated data protocol.

Abstract: A modem operable to communicate information from a communications link to a host using a universal serial bus includes a modem memory operable to store a plurality of ATM cells. The modem also includes a receive manager operable to receive a plurality of ATM cells from the communications link and to store the ATM cell in the modem memory. The receive manager further operates to format the ATM cells into universal serial bus packets, and to transmit each universal serial bus packet to the host as soon as the packet is full. The modem further includes a short packet instigator operable to determine whether each ATM cell contains a termination condition associated with the content of the ATM cell, and in response to determining that an ATM cell contains a termination condition, to instigate transmission of a short packet comprising a universal serial bus packet carrying less than its capacity.

Abstract: A transmit scheduler and method of operation are provided for an asynchronous transfer mode network. The transmit scheduler is operable to write data to and read data from a scheduler table and a virtual channel identifier ("VCI") table in order to schedule cells for virtual channels. The transmit scheduler calculates a location in the scheduler table in which to schedule a cell for a current virtual channel and determines whether a cell for a prior virtual channel is scheduled in the calculated location in the scheduler table. The transmit scheduler then schedules the cell for the current virtual channel at the calculated location in the scheduler table. If a cell for a prior virtual channel was scheduled in the calculated location in the scheduler table, the transmit scheduler writes a pointer into a next pointer field of a record for the current virtual channel in the VCI table, where the pointer provides a link to a record for the prior virtual channel in the VCI table.

Abstract: An ATM adapter for desktop applications includes an adapter for interfacing an ATM network. The adapter includes an ATM application specific integrated circuit (ASIC). The ATM ASIC may interface with a data bus such as an SBus using a host interface circuit. The host interface circuit includes a bus interface, a DMA controller and a slave access controller. The DMA controller controls DMA operations within the ATM ASIC and associates with a RAM interface arbiter. The slave access controller controls operation of an interrupt circuit that goes to the SBus as well as a statistics circuit. The RAM interface arbiter arbitrates communication between the DMA controller, the slave access control circuit, a segmentation engine, and a reassembly engine. The RAM interface arbiter communicates with the RAM bus to a RAM associated with an adapter. The segmentation engine segments data into ATM format for transfer through a physical interface circuit.