Patents by Inventor Klaus Scheibert
Klaus Scheibert has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11705987Abstract: An apparatus for handling an incoming communication data frame containing a plurality of bits is provided. The apparatus may include a plurality of data matchers, each data matcher configured to compare a subset of the plurality of bits of the communication data frame with a predetermined data pattern of a plurality of data patterns and to provide a data matcher output to indicate the result of the data matcher comparison, a plurality of selectors, each selector configured to compare a subset of the data matcher outputs of the plurality of data matchers with a predetermined selection pattern of a plurality of selection patterns and to provide a selector output to indicate the result of the selector comparison, and a frame filter configured to transfer the incoming frame to application logic only if the selector outputs of the plurality of selectors match a predetermined filter pattern, and to also transfer the selector outputs of the plurality of selectors to the application logic.Type: GrantFiled: May 28, 2021Date of Patent: July 18, 2023Assignee: Infineon Technologies AGInventors: Wai Keung Frankie Chan, Klaus Scheibert, Harald Zweck
-
Patent number: 11308240Abstract: A method for cryptographic data processing by means of a circuit comprises using a first circuit section to perform a first cryptographic operation in order to obtain first cryptographic data. The method further includes transmitting the first cryptographic data to a second circuit section via a transmission area of the circuit that physically separates the second circuit section from the first circuit section and whose resistance to attacks is at most as high as the resistance of the first circuit section. The method includes using the second circuit section to perform a second cryptographic operation using the first cryptographic data in order to obtain second cryptographic data.Type: GrantFiled: August 1, 2018Date of Patent: April 19, 2022Assignee: Infineon Technologies AGInventors: Alexander Zeh, Viola Rieger, Klaus Scheibert
-
Publication number: 20210376954Abstract: An apparatus for handling an incoming communication data frame containing a plurality of bits is provided. The apparatus may include a plurality of data matchers, each data matcher configured to compare a subset of the plurality of bits of the communication data frame with a predetermined data pattern of a plurality of data patterns and to provide a data matcher output to indicate the result of the data matcher comparison, a plurality of selectors, each selector configured to compare a subset of the data matcher outputs of the plurality of data matchers with a predetermined selection pattern of a plurality of selection patterns and to provide a selector output to indicate the result of the selector comparison, and a frame filter configured to transfer the incoming frame to application logic only if the selector outputs of the plurality of selectors match a predetermined filter pattern, and to also transfer the selector outputs of the plurality of selectors to the application logic.Type: ApplicationFiled: May 28, 2021Publication date: December 2, 2021Inventors: Wai Keung Frankie Chan, Klaus Scheibert, Harald Zweck
-
Publication number: 20190050601Abstract: A method for cryptographic data processing by means of a circuit comprises using a first circuit section to perform a first cryptographic operation in order to obtain first cryptographic data. The method further includes transmitting the first cryptographic data to a second circuit section via a transmission area of the circuit that physically separates the second circuit section from the first circuit section and whose resistance to attacks is at most as high as the resistance of the first circuit section. The method includes using the second circuit section to perform a second cryptographic operation using the first cryptographic data in order to obtain second cryptographic data.Type: ApplicationFiled: August 1, 2018Publication date: February 14, 2019Inventors: Alexander Zeh, Viola Reiger, Klaus Scheibert
-
Patent number: 9672182Abstract: Methods and systems for transferring a high-speed data signal between more than two electronic devices within a system comprising a master device and a plurality of slave devices are presented. The master device and the plurality of slave devices are connected through high-speed links between high-speed interfaces, thereby forming a closed ring. The high-speed interfaces are comprised by the master device and each of the plurality of slave devices, respectively. A common low frequency clock signal is provided by the master device to each of the slave devices, and a high-speed interface communication method for communication between the master device and the plurality of slave devices through the high-speed links is used.Type: GrantFiled: August 21, 2014Date of Patent: June 6, 2017Assignee: Infineon Technologies AGInventors: Axel Freiwald, Klaus Scheibert
-
Publication number: 20160055114Abstract: Methods and systems for transferring a high-speed data signal between more than two electronic devices within a system comprising a master device and a plurality of slave devices are presented. The master device and the plurality of slave devices are connected through high-speed links between high-speed interfaces, thereby forming a closed ring. The high-speed interfaces are comprised by the master device and each of the plurality of slave devices, respectively. A common low frequency clock signal is provided by the master device to each of the slave devices, and a high-speed interface communication method for communication between the master device and the plurality of slave devices through the high-speed links is used.Type: ApplicationFiled: August 21, 2014Publication date: February 25, 2016Inventors: Axel Freiwald, Klaus Scheibert
-
Patent number: 8799703Abstract: Some embodiments of the invention relate to an embedded processing system. The system includes a memory unit to store a plurality of operating instructions and a processing unit coupled to the memory unit. The processing unit can execute logical operations corresponding to respective operating instructions. An input/output (I/O) interface receives a first time-varying waveform and provides an I/O signal that is based on the first time-varying waveform. A comparison unit coupled to the processing unit and adapted to selectively assert an error signal based on whether the I/O signal has a predetermined relationship with a reference signal, wherein the predetermined relationship holds true during normal operation but fails to hold true when an unexpected event occurs and causes an unexpected change at least one of the I/O signal and reference signal.Type: GrantFiled: September 16, 2013Date of Patent: August 5, 2014Assignee: Infineon Technologies AGInventors: Simon Brewerton, Patrick Leteinturier, Oreste Bernardi, Antonio Vilela, Klaus Scheibert, Jens Barrenscheen
-
Publication number: 20140019805Abstract: Some embodiments of the invention relate to an embedded processing system. The system includes a memory unit to store a plurality of operating instructions and a processing unit coupled to the memory unit. The processing unit can execute logical operations corresponding to respective operating instructions. An input/output (I/O) interface receives a first time-varying waveform and provides an I/O signal that is based on the first time-varying waveform. A comparison unit coupled to the processing unit and adapted to selectively assert an error signal based on whether the I/O signal has a predetermined relationship with a reference signal, wherein the predetermined relationship holds true during normal operation but fails to hold true when an unexpected event occurs and causes an unexpected change at least one of the I/O signal and reference signal.Type: ApplicationFiled: September 16, 2013Publication date: January 16, 2014Applicant: Infineon Technologies AGInventors: Simon Brewerton, Patrick Leteinturier, Oreste Barnardi, Antonio Vilela, Klaus Scheibert, Jens Barrenscheen
-
Patent number: 8539278Abstract: Some embodiments of the invention relate to an embedded processing system. The system includes a memory unit to store a plurality of operating instructions and a processing unit coupled to the memory unit. The processing unit can execute logical operations corresponding to respective operating instructions. An input/output (I/O) interface receives a first time-varying waveform and provides an I/O signal that is based on the first time-varying waveform. A comparison unit coupled to the processing unit and adapted to selectively assert an error signal based on whether the I/O signal has a predetermined relationship with a reference signal, wherein the predetermined relationship holds true during normal operation but fails to hold true when an unexpected event occurs and causes an unexpected change at least one of the I/O signal and reference signal.Type: GrantFiled: October 29, 2010Date of Patent: September 17, 2013Assignee: Infineon Technologies AGInventors: Simon Brewerton, Patrick Leteinturier, Oreste Bernardi, Antonio Vilela, Klaus Scheibert, Jens Barrenscheen
-
Publication number: 20120110374Abstract: Some embodiments of the invention relate to an embedded processing system. The system includes a memory unit to store a plurality of operating instructions and a processing unit coupled to the memory unit. The processing unit can execute logical operations corresponding to respective operating instructions. An input/output (I/O) interface receives a first time-varying waveform and provides an I/O signal that is based on the first time-varying waveform. A comparison unit coupled to the processing unit and adapted to selectively assert an error signal based on whether the I/O signal has a predetermined relationship with a reference signal, wherein the predetermined relationship holds true during normal operation but fails to hold true when an unexpected event occurs and causes an unexpected change at least one of the I/O signal and reference signal.Type: ApplicationFiled: October 29, 2010Publication date: May 3, 2012Applicant: Infineon Technologies AGInventors: Simon Brewerton, Patrick Leteinturier, Oreste Bernardi, Antonio Vilela, Klaus Scheibert, Jens Barrenscheen
-
Patent number: 7743295Abstract: A system and method for testing an integrated circuit is disclosed. One embodiment includes at least one central processing unit, at least one volatile memory area, and an interface, wherein the volatile memory area is connected to the interface to be written thereto by the interface. The system includes a test device connected with the integrated circuit which is configured to stop the program execution, write data in the volatile memory by using the interface, and start the program execution.Type: GrantFiled: March 14, 2007Date of Patent: June 22, 2010Assignee: Infineon Technologies AGInventors: Albrecht Mayer, Klaus Scheibert, Harry Siebert
-
Publication number: 20070220336Abstract: A system and method for testing an integrated circuit is disclosed. One embodiment includes at least one central processing unit, at least one volatile memory area, and an interface is suggested, wherein the memory area is adapted to be written by the interface. The system includes a test device connected with the integrated circuit which is configured to stop the program execution, write data in the volatile memory by using the interface, and start the program execution.Type: ApplicationFiled: March 14, 2007Publication date: September 20, 2007Applicant: INFINEON TECHNOLOGIES AGInventors: Albrecht Mayer, Klaus Scheibert, Harry Siebert