Patents by Inventor Klaus Schuegraf
Klaus Schuegraf has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10679723Abstract: Disclosed is a system and method for performing direct memory characterization of memory cells in a memory array using peripheral transistors. A memory array is fabricated using a mask layer defining routing for a set of first stage periphery transistors electrically connected to the word lines of the memory array. A revised mask is used for defining a different routing for a set of second stage periphery transistors including different characteristics than the first stage periphery transistors. Testing is conducted by applying a simulated Erase signal to the nonvolatile memory cells and determining which cells are erased. Based on this test, certain characteristics of the first and/or second stage periphery transistors can be identified that provide improved conditions for the nonvolatile memory cells. A product chip can be manufactured using modified versions of the first stage periphery transistors that incorporate the characteristics that provide the improved condition(s).Type: GrantFiled: December 6, 2018Date of Patent: June 9, 2020Assignee: PDF SOLUTIONS, INC.Inventors: Dong Kyu Lee, Kelvin Yih-Yuh Doong, Tuan Pham, Klaus Schuegraf, Christoph Dolainsky, Huan Tsung Huang, Hendrik Schneider
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Patent number: 9502294Abstract: A method of singulating a plurality of semiconductor dies includes providing a carrier substrate and joining a semiconductor substrate to the carrier substrate. The semiconductor substrate includes a plurality of devices. The method also includes forming a mask layer on the semiconductor substrate, exposing a predetermined portion of the mask layer to light, and processing the predetermined portion of the mask layer to form a predetermined mask pattern on the semiconductor substrate. The method further includes forming the plurality of semiconductor dies, each of the plurality of semiconductor dies being associated with the predetermined mask pattern and including one or more of the plurality of devices and separating the plurality of semiconductor dies from the carrier substrate.Type: GrantFiled: November 8, 2013Date of Patent: November 22, 2016Assignee: Applied Materials, Inc.Inventors: Klaus Schuegraf, Seshadri Ramaswami, Michael R. Rice, Mohsen S. Salek, Claes H. Bjorkman
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Patent number: 9232569Abstract: Apparatus for providing pulsed or continuous energy in a process chamber are provided herein. The apparatus may include a lamphead including a set of lamps, wherein the first set of lamps are not solid state light sources, and a set of solid state light sources disposed on the lamp head, to provide pulsed or continuous energy to the process chamber.Type: GrantFiled: February 27, 2013Date of Patent: January 5, 2016Assignee: APPLIED MATERIALS, INC.Inventors: Joseph Johnson, John Gerling, Klaus Schuegraf
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Patent number: 8994089Abstract: In some embodiments, an interlayer polysilicon dielectric cap disposed atop a substrate having a first floating gate, a second floating gate and an isolation layer disposed between the first floating gate and the second floating gate may include: a first nitrogen containing layer disposed atop an upper portion and sidewalls of the first floating gate and second floating gate; a first oxygen containing layer disposed atop the first nitrogen containing layer and an upper surface of the isolation layer; a second nitrogen containing layer disposed atop an upper portion and sidewalls of the first oxygen containing layer; and a second oxygen containing layer disposed atop the second nitrogen containing layer and an upper surface of the first oxygen containing layer.Type: GrantFiled: November 11, 2011Date of Patent: March 31, 2015Assignee: Applied Materials, Inc.Inventors: Matthew S. Rogers, Klaus Schuegraf
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Patent number: 8853763Abstract: Semiconductor devices are provided with encapsulating films for protection of sidewall features during fabrication processes, such as etching to form isolation regions. In a non-volatile flash memory, for example, a trench isolation process is divided into segments to incorporate an encapsulating film along the sidewalls of charge storage material. A pattern is formed over the layer stack followed by etching the charge storage material to form strips elongated in the column direction across the substrate, with a layer of tunnel dielectric material therebetween. Before etching the substrate, an encapsulating film is formed along the sidewalls of the strips of charge storage material. The encapsulating film can protect the sidewalls of the charge storage material during subsequent cleaning, oxidation and etch processes. In another example, the encapsulating film is simultaneously formed while etching to form strips of charge storage material and the isolation trenches.Type: GrantFiled: September 7, 2012Date of Patent: October 7, 2014Assignee: SanDisk Technologies Inc.Inventors: Tuan Pham, Sanghyun Lee, Masato Horiike, Klaus Schuegraf, Masaaki Higashitani, Keiichi Isono
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Publication number: 20140238970Abstract: Apparatus for providing pulsed or continuous energy in a process chamber are provided herein. The apparatus may include a lamphead including a set of lamps, wherein the first set of lamps are not solid state light sources, and a set of solid state light sources disposed on the lamp head, to provide pulsed or continuous energy to the process chamber.Type: ApplicationFiled: February 27, 2013Publication date: August 28, 2014Applicant: APPLIED MATERIALS, INC.Inventors: JOSEPH JOHNSON, JOHN GERLING, KLAUS SCHUEGRAF
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Publication number: 20140196850Abstract: A method of singulating a plurality of semiconductor dies includes providing a carrier substrate and joining a semiconductor substrate to the carrier substrate. The semiconductor substrate includes a plurality of devices. The method also includes forming a mask layer on the semiconductor substrate, exposing a predetermined portion of the mask layer to light, and processing the predetermined portion of the mask layer to form a predetermined mask pattern on the semiconductor substrate. The method further includes forming the plurality of semiconductor dies, each of the plurality of semiconductor dies being associated with the predetermined mask pattern and including one or more of the plurality of devices and separating the plurality of semiconductor dies from the carrier substrate.Type: ApplicationFiled: November 8, 2013Publication date: July 17, 2014Applicant: APPLIED MATERIALS, INC.Inventors: Klaus Schuegraf, Seshadri Ramaswami, Michael R. Rice, Mohsen S. Salek, Claes H. Bjorkman
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Patent number: 8709953Abstract: Ultrathin material layers are plasma etched with an etch system configured for cryogenic cooling of a substrate to reduce the diffusion coefficients of foreign and intrinsic stop layer atoms (e.g., of the bombarded crystal lattice), and further configured for plasma pulsing to reduce the energy of the impinging ions with cryogenic wafer temperatures. Substrate temperatures of ?50° C. or more are employed to reduce the susceptibility of a stop layer material to damage associated with ion impact. Ion energy is reduced to below the threshold where stop layer lattice atoms are displaced or ions are implanted into the bulk lattice. In embodiments, a plasma of an etchant gas having ion energies less than 10 eV are achieved through plasma pulsing, which when directed at the low temperature substrate may controllably etch ultra-thin material layers.Type: GrantFiled: October 17, 2012Date of Patent: April 29, 2014Assignee: Applied Materials, Inc.Inventors: Thorsten Lill, Klaus Schuegraf, Dmitry Lubomirsky
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Patent number: 8637845Abstract: Optimized electrodes for ReRAM memory cells and methods for forming the same are discloses. One aspect comprises forming a first electrode, forming a state change element in contact with the first electrode, treating the state change element, and forming a second electrode. Treating the state change element increases the barrier height at the interface between the second electrode and the state change element. Another aspect comprises forming a first electrode in a manner to deliberately establish a certain degree of amorphization in the first electrode, forming a state change element in contact with the first electrode. The degree of amorphization of the first electrode is either at least as great as the degree of amorphization of the state change element or no more than 5 percent less than the degree of amorphization of the state change element.Type: GrantFiled: July 19, 2012Date of Patent: January 28, 2014Assignee: SanDisk 3D LLCInventors: Deepak C. Sekar, April Schricker, Xiying Chen, Klaus Schuegraf
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Patent number: 8580615Abstract: A method of singulating a plurality of semiconductor dies includes providing a carrier substrate and joining a semiconductor substrate to the carrier substrate. The semiconductor substrate includes a plurality of devices. The method also includes forming a mask layer on the semiconductor substrate, exposing a predetermined portion of the mask layer to light, and processing the predetermined portion of the mask layer to form a predetermined mask pattern on the semiconductor substrate. The method further includes forming the plurality of semiconductor dies, each of the plurality of semiconductor dies being associated with the predetermined mask pattern and including one or more of the plurality of devices and separating the plurality of semiconductor dies from the carrier substrate.Type: GrantFiled: February 17, 2012Date of Patent: November 12, 2013Assignee: Applied Materials, Inc.Inventors: Klaus Schuegraf, Seshadri Ramaswami, Michael R. Rice, Mohsen S. Salek, Claes H. Bjorkman
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Patent number: 8498146Abstract: A storage system and method for operating the storage system that uses reversible resistance-switching elements is described. Techniques are disclosed herein for varying programming conditions to account for different resistances that memory cells have. These techniques can program memory cells in fewer attempts, which can save time and/or power. Techniques are disclosed herein for achieving a high programming bandwidth while reducing the worst case current and/or power consumption.Type: GrantFiled: February 15, 2012Date of Patent: July 30, 2013Assignee: SanDisk 3D LLCInventors: Deepak C. Sekar, Klaus Schuegraf, Roy Scheuerlein
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Publication number: 20130119451Abstract: In some embodiments, an interlayer polysilicon dielectric cap disposed atop a substrate having a first floating gate, a second floating gate and an isolation layer disposed between the first floating gate and the second floating gate may include: a first nitrogen containing layer disposed atop an upper portion and sidewalls of the first floating gate and second floating gate; a first oxygen containing layer disposed atop the first nitrogen containing layer and an upper surface of the isolation layer; a second nitrogen containing layer disposed atop an upper portion and sidewalls of the first oxygen containing layer; and a second oxygen containing layer disposed atop the second nitrogen containing layer and an upper surface of the first oxygen containing layer.Type: ApplicationFiled: November 11, 2011Publication date: May 16, 2013Applicant: APPLIED MATERIALS, INC.Inventors: MATTHEW S. ROGERS, KLAUS SCHUEGRAF
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Publication number: 20130109190Abstract: Ultrathin material layers are plasma etched with an etch system configured for cryogenic cooling of a substrate to reduce the diffusion coefficients of foreign and intrinsic stop layer atoms (e.g., of the bombarded crystal lattice), and further configured for plasma pulsing to reduce the energy of the impinging ions with cryogenic wafer temperatures. Substrate temperatures of ?50° C. or more are employed to reduce the susceptibility of a stop layer material to damage associated with ion impact. Ion energy is reduced to below the threshold where stop layer lattice atoms are displaced or ions are implanted into the bulk lattice. In embodiments, a plasma of an etchant gas having ion energies less than 10 eV are achieved through plasma pulsing, which when directed at the low temperature substrate may controllably etch ultra-thin material layers.Type: ApplicationFiled: October 17, 2012Publication date: May 2, 2013Inventors: Thorsten LILL, Klaus SCHUEGRAF, Dmitry LUBOMIRSKY
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Publication number: 20130045570Abstract: A method of singulating a plurality of semiconductor dies includes providing a carrier substrate and joining a semiconductor substrate to the carrier substrate. The semiconductor substrate includes a plurality of devices. The method also includes forming a mask layer on the semiconductor substrate, exposing a predetermined portion of the mask layer to light, and processing the predetermined portion of the mask layer to form a predetermined mask pattern on the semiconductor substrate. The method further includes forming the plurality of semiconductor dies, each of the plurality of semiconductor dies being associated with the predetermined mask pattern and including one or more of the plurality of devices and separating the plurality of semiconductor dies from the carrier substrate.Type: ApplicationFiled: February 17, 2012Publication date: February 21, 2013Applicant: Applied Materials, Inc.Inventors: Klaus Schuegraf, Seshadri Ramaswami, Michael R. Rice, Mohsen S. Salek, Claes H. Bjorkman
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Publication number: 20120326220Abstract: Semiconductor devices are provided with encapsulating films for protection of sidewall features during fabrication processes, such as etching to form isolation regions. In a non-volatile flash memory, for example, a trench isolation process is divided into segments to incorporate an encapsulating film along the sidewalls of charge storage material. A pattern is formed over the layer stack followed by etching the charge storage material to form strips elongated in the column direction across the substrate, with a layer of tunnel dielectric material therebetween. Before etching the substrate, an encapsulating film is formed along the sidewalls of the strips of charge storage material. The encapsulating film can protect the sidewalls of the charge storage material during subsequent cleaning, oxidation and etch processes. In another example, the encapsulating film is simultaneously formed while etching to form strips of charge storage material and the isolation trenches.Type: ApplicationFiled: September 7, 2012Publication date: December 27, 2012Inventors: Tuan Pham, Sanghyun Lee, Masato Horiike, Klaus Schuegraf, Masaaki Higashitani, Keiichi Isono
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Publication number: 20120280201Abstract: Optimized electrodes for ReRAM memory cells and methods for forming the same are discloses. One aspect comprises forming a first electrode, forming a state change element in contact with the first electrode, treating the state change element, and forming a second electrode. Treating the state change element increases the barrier height at the interface between the second electrode and the state change element. Another aspect comprises forming a first electrode in a manner to deliberately establish a certain degree of amorphization in the first electrode, forming a state change element in contact with the first electrode. The degree of amorphization of the first electrode is either at least as great as the degree of amorphization of the state change element or no more than 5 percent less than the degree of amorphization of the state change element.Type: ApplicationFiled: July 19, 2012Publication date: November 8, 2012Inventors: Deepak C. Sekar, April Schricker, Xiying Chen, Klaus Schuegraf
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Patent number: 8288293Abstract: Semiconductor devices are provided with encapsulating films for protection of sidewall features during fabrication processes, such as etching to form isolation regions. In a non-volatile flash memory, for example, a trench isolation process is divided into segments to incorporate an encapsulating film along the sidewalls of charge storage material. A pattern is formed over the layer stack followed by etching the charge storage material to form strips elongated in the column direction across the substrate, with a layer of tunnel dielectric material therebetween. Before etching the substrate, an encapsulating film is formed along the sidewalls of the strips of charge storage material. The encapsulating film can protect the sidewalls of the charge storage material during subsequent cleaning, oxidation and etch processes. In another example, the encapsulating film is simultaneously formed while etching to form strips of charge storage material and the isolation trenches.Type: GrantFiled: April 20, 2010Date of Patent: October 16, 2012Assignee: SanDisk Technologies Inc.Inventors: Tuan Pham, Sanghyun Lee, Masato Horiike, Klaus Schuegraf, Masaaki Higashitani, Keiichi Isono
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Patent number: 8263420Abstract: Optimized electrodes for ReRAM memory cells and methods for forming the same are discloses. One aspect comprises forming a first electrode, forming a state change element in contact with the first electrode, treating the state change element, and forming a second electrode. Treating the state change element increases the barrier height at the interface between the second electrode and the state change element. Another aspect comprises forming a first electrode in a manner to deliberately establish a certain degree of amorphization in the first electrode, forming a state change element in contact with the first electrode. The degree of amorphization of the first electrode is either at least as great as the degree of amorphization of the state change element or no more than 5 percent less than the degree of amorphization of the state change element.Type: GrantFiled: February 3, 2009Date of Patent: September 11, 2012Assignee: SanDisk 3D LLCInventors: Depak C. Sekar, April Schricker, Xiying Chen, Klaus Schuegraf, Raghuveer Makala
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Publication number: 20120202316Abstract: Embodiments of the invention generally provide methods for forming a silicon-based photovoltaic (PV) device containing a transparent conductive oxide (TCO) layer that is exposed to a very high frequency (VHF) plasma. In one embodiment, a method includes depositing a TCO layer on an underlying surface, such as a transparent substrate, and exposing the TCO layer to a VHF plasma to form a treated surface on the TCO layer during a plasma treatment process. The VHF plasma is generated by ionizing a process gas containing hydrogen (H2) and nitrous oxide at an excitation frequency within a range from about 30 MHz to about 300 MHz. The method further includes forming a p-i-n junction over the TCO layer, wherein the p-i-n junction contains a p-type Si-based layer disposed on the treated surface of the TCO layer. In some examples, the TCO layer contains zinc oxide and the p-i-n junction contains amorphous silicon.Type: ApplicationFiled: January 27, 2012Publication date: August 9, 2012Applicant: APPLIED MATERIALS, INC.Inventors: KHALED AHMED, Klaus Schuegraf
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Publication number: 20120147657Abstract: A storage system and method for operating the storage system that uses reversible resistance-switching elements is described. Techniques are disclosed herein for varying programming conditions to account for different resistances that memory cells have. These techniques can program memory cells in fewer attempts, which can save time and/or power. Techniques are disclosed herein for achieving a high programming bandwidth while reducing the worst case current and/or power consumption.Type: ApplicationFiled: February 15, 2012Publication date: June 14, 2012Inventors: Deepak C. Sekar, Klaus Schuegraf, Roy Scheuerlein