Abstract: An integrated circuit module including at least one semiconductor chip. The at least one semiconductor chip includes a plurality of voltage converters and switching circuitry for connecting an input terminal of one of the plurality of voltage converters to an input power supply rail and an output terminal of at least one of the plurality of voltage converters to an output supply rail. The switching circuitry is, dependent on at least one input signal, operable for selectively establishing for at least two of the plurality of voltage converters one out of the group including a parallel connection of the at least two voltage converters, a serially cascaded connection of the at least two voltage converters, and a stacked serial connection of the at least two voltage converters.

Abstract: A method to avoid malconnections with respect to voltage levels of electronic components of a circuit board during circuit board design is described, comprising the steps of: creation of a Component Specification Library (CSL) comprising at least distinct pinnames and assigned voltage data; creation of groups of pins of components to be connected with each other on a particular voltage level according to the circuit board design; verification of the voltage data of the pins of the components within the particular group.

Abstract: A method to avoid malconnections with respect to voltage levels of electronic components of a circuit board during circuit board design is described, comprising the steps of: creation of a Component Specification Library (CSL) comprising at least distinct pinnames and assigned voltage data; creation of groups of pins of components to be connected with each other on a particular voltage level according to the circuit board design; verification of the voltage data of the pins of the components within the particular group.

Abstract: A method and system of accessing memory cells within a dynamic hardware memory block operated with a bitline precharge circuit, in which differential read/write access operations are performed by activating complementary bitlines. A reduction in power dissipation is realized by determining whether a next access operation following a current access operation is a read or write access, and performing a precharge of the bitlines of the array only when a read operation follows the current access operation. A conventional precharge control signal is combined with an external control signal indicating if the next cycle is a read cycle. The combination of the two signals can be used, for example, as input to a simple AND gate to generate an effective precharge signal. The effective precharge signal permits precharging of bitlines only when those bitlines are used for read access in a respective next cycle.

Abstract: The present invention relates to the field of hardware logic circuits and in particular to dynamic hardware logic implemented in computer processors, and more particularly, to an integrated circuit comprising a dynamic logic function implementing a predetermined logic function with a plurality of transistor stacks, the integrated circuit comprising a precharge node at the input of said logic function implementation, an output latch connected to the output node of said logic function for stabilizing the result of the evaluation of said logic function. The present invention provides such integrated dynamic circuit with a latch, which is protected against instability even in situations involving complex logic functions which are evaluated and their output states are saved by said output latch.

Abstract: The present invention relates to the field of hardware logic circuits and in particular to dynamic hardware logic implemented in computer processors, and more particularly, to an integrated circuit comprising a dynamic logic function implementing a predetermined logic function with a plurality of transistor stacks, the integrated circuit comprising a precharge node at the input of said logic function implementation, an output latch connected to the output node of said logic function for stabilizing the result of the evaluation of said logic function. The present invention provides such integrated dynamic circuit with a latch, which is protected against instability even in situations involving complex logic functions which are evaluated and their output states are saved by said output latch.

Abstract: The present invention relates to computer hardware and in particular to power management of high frequency storage designs, which are able to implement differential write or read access in a dynamic hardware arrangement of storage cells having some inner segmentation. More particularly, the present invention relates to a method and respective system of accessing memory cells within a dynamic hardware memory block operated with a bitline precharge circuit, in which differential read/write access operations are performed by activating complementary bitlines. A reduction in power dissipation is realized by determining whether an access operation following a current access operation is a read or write access, and performing a precharge of the bitlines of the array only when a read operation follows the current access operation. A conventional precharge control signal (20) is combined with an external control signal (22) indicating if the next cycle is a read cycle.

Abstract: A cable connector assembly and method for making, wherein the assembly connects to a flat ribbon cable having a plurality of conductors and electrical insulation about the conductors. The cable connector assembly includes a plurality of electrical contacts, each including a terminal configured to connect to at least one of the conductors of the flat ribbon cable directly through the electrical insulation to form an electrical junction. Each contact is configured to electrically connect to an external member. The cable connector assembly has a housing for holding the contacts arranged in a first row and as second row where the contacts in the rows form a grid and are connected in an offset manner to minimize cross talk.

Abstract: Hence, according to the present invention a cable connector assembly for being connected to a flat ribbon cable including a plurality of conductors and electrical insulation about said conductors maintaining the latter electrically insulated from each other. The cable connector assembly comprises a plurality of electrical contacts, each including terminal means being configured to connect at least one of said conductors directly through said electrical insulation to form an electrical junction, and contacting means on each of said electrical contacts being configured to electrically connect each of said electrical contacts to an external member. It further comprises a housing for holding said contacting means arranged in a first row and a second row forming an orthogonal grid.

Abstract: Apparatus and method for stacking bundles of sheets onto a table top or the like, and with the bundles being stacked in an interlocked manner where, in all layers of the bundles, the bundles have right angled relationships with each other, for sturdy and secure positioning of the bundles in the stack. A rotatable table is utilized for supporting the bundles, and a transport or carrier, such as an overhead crane, is utilized for bringing the bundles onto the table where, after a few bundles are placed thereon, the table is rotated and displaced and additional bundles are then placed onto the table for the interlocked relationship of all of the bundles.

Abstract: A method and apparatus for handling a stack of sheets, including the stacking of the sheets from a continuous incoming stream of sheets and on a lower endboard, and compressing the stack and restricting the sides of the stack while the stack is moved laterally to a station where an upper endboard is applied and the stack is strapped or bound and then moved further away.