Abstract: An integrated circuit demodulator component contains a demodulator circuit (90), a first input (12) and an output (30) connected to the demodulator circuit (90). Furthermore the demodulator component (10) has a second input (18) and a multiplexer (80), which is controlled by a selector signal at a selector input (110). The multiplexer optionally connects the first input (12) or the second input (18) to the demodulator circuit (90). This permits a test of the integrated circuit demodulator component (10) during operation with operational signals. To this end, a signal from a modulator component (148) is applied to the second input (18) through a test feedback loop (210). A processor (142) compares the output signal of the integrated circuit demodulator component (10) at a receiver (174) with a signal transmitted by a transmitter (178). In the case of non-identity, either the modulator component (148) or the demodulator component (10) is defective.

Abstract: To establish an inexpensive, and universally applicable power controller for the monitored activation, monitoring and protection of current-consuming loads by a microprocessor having low-power control outputs, the following circuit elements are implemented in an integrated device: an activation path (12) disconnectable by an electronic switch (18) and to which a C-MOS/TTL-signal is adapted to be applied by a microprocessor output port and which generates a MOS-FET control signal; a latch (20) which is arranged to control said electronic switch (18) and which, for its part, is adapted to be controled by external C-MOS/TTL-signals such that the switch (18) opens with a first signal and closes with a second signal; a current comparator (40) offering a first and a second switching threshold adapted to be determined by external components and a third fixed internal switching threshold and to which the load current is adapted to be applied common mode rejected and which are arranged to control the latch (20) to ope

Abstract: A frequency-to-digital converter is constructed as an integrated device in which the following functions are implemented: a processor bus interface (38) having data, address and control lines; at least one converter channel (10) having at least one clock generator (24), at least one input (12,14), frequency-to-digital converter means (18), a comparator (44) for comparing a digital frequency equivalent with a programmed digital word (limit value register (48)) and which is arranged to signal the exceeding of a limit value at an output (56) of the device through a programmable time-counter (50) (delay register (124)) as well as a status memory (flip-flop 52) and means (54) for the internal gating of external states, a command register (58) which is arranged to determine and initiate the conversion mode, a range register which is arranged to determine the conversion range (frequency range 22) as well as the test frequency (66) and a output frequency (67), and a status register (88) which is arranged to output in