Abstract: A complementary metal oxide (CMOS) integrated circuit configured for reducing the formation of silicon defects in its silicon substrate during manufacture. The silicon defects are formed from silicon interstitials present in the silicon substrate. The CMOS integrated circuit includes a deep implantation region formed within the silicon substrate. There is further included at least one vertical trench formed in the silicon substrate. The trench is formed such that at least a portion of the trench penetrates into the deep implantation region of the silicon substrate to present vertical surfaces within the deep implantation region, thereby allowing the silicon interstitials to recombine at the vertical surfaces.