Abstract: A process is disclosed for fabricating a CMOS structure with ESD protection. The outside transistors are covered with a protective oxide layer which is so masked as to cover the areas of the respective source and drain regions adjoining the field-oxide regions and the gate regions. The protective oxide layer is then subjected to a heat treatment, after which a siliciding process is carried out.

Abstract: A method of fabricating CMOS devices with local interconnects is disclosed which is performed in two stages. In the first stage, a SALICIDE process is carried out, and in the second stage, the local interconnects are formed.

Abstract: A counter for the non-volatile storage of an n-bit word includes a storage matrix having 2.sup.m non-volatile electrically programmable storage elements which may be bitwise selected by means of a word shift register and a bit shift register, a binary counter having m+n bistable flip-flops, with each one of the n Most Significant Bit flip-flops being coupled to a storage cell of a non-volatile storage device, and a clock sequence control for providing reset, erase and write pulses.

Abstract: A circuit arrangement is provided to supervise the supply voltage of the programming logic of a non-volatile integrated circuit comprising insulated-gate field-effect transistors whose threshold voltages are altered by the programming logic and whose gate electrodes are connected wordwise to word lines. The circuit arrangement is integrated into the integrated circuit and includes an integrated threshold switch connected to the programming voltage source and a reference voltage source having at least one, but preferably two zener diodes connected in series. The threshold switch in combination with supervision logic connects the word lines to the substrate voltage of the programming logic when the supply voltage is lost. An additional threshold switch coupled to the supervision logic, the reference voltage source and the programming voltage line connects the word lines to the substrate voltage of the programming logic when the programming voltage is lost.

Abstract: This invention relates to a bucket brigade circuit or delay line wherein there is provided frequency-dependent compensation of the signal attenuation after n-stages of the circuit. The compensation circuit contains a differential amplifier and a transferring circuit adding the frequency dependent signal loss to the bucket brigade line signal. The differential amplifier samples the signal of two adjacent stages controlled by the same clock signal phase.