Patents by Inventor Klemens Kordik
Klemens Kordik has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10970163Abstract: A frequency signal generator includes a controllable oscillator unit, a frequency control unit and an error detection unit. The controllable oscillator unit generates and provides a frequency signal. The frequency control unit generates a frequency control signal and the controllable oscillator unit varies a frequency of the frequency signal based on the frequency control signal. Further, the error detection unit receives the frequency control signal, detects an error within the frequency control signal and provides an error signal. The error signal comprises information on a detected error.Type: GrantFiled: September 20, 2019Date of Patent: April 6, 2021Assignee: Infineon Technologies AGInventors: Bernhard Gstoettenbauer, Klemens Kordik
-
Publication number: 20200012556Abstract: A frequency signal generator includes a controllable oscillator unit, a frequency control unit and an error detection unit. The controllable oscillator unit generates and provides a frequency signal. The frequency control unit generates a frequency control signal and the controllable oscillator unit varies a frequency of the frequency signal based on the frequency control signal. Further, the error detection unit receives the frequency control signal, detects an error within the frequency control signal and provides an error signal. The error signal comprises information on a detected error.Type: ApplicationFiled: September 20, 2019Publication date: January 9, 2020Inventors: Bernhard Gstoettenbauer, Klemens Kordik
-
Patent number: 10459784Abstract: A frequency signal generator includes a controllable oscillator unit, a frequency control unit and an error detection unit. The controllable oscillator unit generates and provides a frequency signal. The frequency control unit generates a frequency control signal and the controllable oscillator unit varies a frequency of the frequency signal based on the frequency control signal. Further, the error detection unit receives the frequency control signal, detects an error within the frequency control signal and provides an error signal. The error signal comprises information on a detected error.Type: GrantFiled: June 28, 2013Date of Patent: October 29, 2019Assignee: Infineon Technologies AGInventors: Bernhard Gstöttenbauer, Klemens Kordik
-
Patent number: 10223507Abstract: A programmable system with program flow monitoring is provided. A memory is configured to store a set of instructions, where the instructions are configured to be executed in a predefined order. A processor is configured to execute the set of instructions by fetching and executing the instructions in the predefined order. A program flow monitoring (PFM) unit is configured to deterministically generate a fingerprint from accesses to the memory, such as instruction fetches, while executing the set of instructions. A verification unit is configured to compare the generated fingerprint to an expected fingerprint to determine whether the set of instructions executed in the predefined order. A method for program flow monitoring, as well as a safety system within which the programmable system finds application, are also provided.Type: GrantFiled: October 28, 2016Date of Patent: March 5, 2019Assignee: Infineon Technologies AGInventor: Klemens Kordik
-
Publication number: 20180121272Abstract: A programmable system with program flow monitoring is provided. A memory is configured to store a set of instructions, where the instructions are configured to be executed in a predefined order. A processor is configured to execute the set of instructions by fetching and executing the instructions in the predefined order. A program flow monitoring (PFM) unit is configured to deterministically generate a fingerprint from accesses to the memory, such as instruction fetches, while executing the set of instructions. A verification unit is configured to compare the generated fingerprint to an expected fingerprint to determine whether the set of instructions executed in the predefined order. A method for program flow monitoring, as well as a safety system within which the programmable system finds application, are also provided.Type: ApplicationFiled: October 28, 2016Publication date: May 3, 2018Inventor: Klemens Kordik
-
Patent number: 9485036Abstract: An RF receiver device includes a semiconductor chip in a chip package, and a test signal generator integrated in the chip. The test signal generator generates an RF test signal including first information. An RF receiver circuit integrated in the chip receives an RF input signal, down-converts the RF input signal into an intermediate frequency (IF) or base band, and digitizes the down-converted signal to obtain a digital signal. An RF receive channel includes a coupler having first and second input ports and an output port. The output port is coupled to the input of the RF receiver circuit, the first input port receives an antenna signal and the second input port receives the test signal from the test signal generator. A signal processor is integrated in the chip and determines, during a test cycle, whether the first information in the digital signal matches a predetermined criterion.Type: GrantFiled: April 14, 2016Date of Patent: November 1, 2016Assignee: Infineon Technologies AGInventors: Klemens Kordik, Rainer Stuhlberger
-
Publication number: 20160233969Abstract: An RF receiver device includes a semiconductor chip in a chip package, and a test signal generator integrated in the chip. The test signal generator generates an RF test signal including first information. An RF receiver circuit integrated in the chip receives an RF input signal, down-converts the RF input signal into an intermediate frequency (IF) or base band, and digitizes the down-converted signal to obtain a digital signal. An RF receive channel includes a coupler having first and second input ports and an output port. The output port is coupled to the input of the RF receiver circuit, the first input port receives an antenna signal and the second input port receives the test signal from the test signal generator. A signal processor is integrated in the chip and determines, during a test cycle, whether the first information in the digital signal matches a predetermined criterion.Type: ApplicationFiled: April 14, 2016Publication date: August 11, 2016Inventors: Klemens Kordik, Rainer Stuhlberger
-
Patent number: 9385700Abstract: A monitor circuit for monitoring a clock signal is described. In accordance with one example of the disclosure, the monitor circuit includes a pulse generator and a comparator circuit. The pulse generator is configured to generate a sequence of pulses synchronous to the clock signal, wherein each pulse has an edge with a monotonously rising or falling signal level. The comparator circuit receives the sequence of pulses and is configured to detect, for each clock cycle of the clock signal, whether or not the signal level of the sequence of pulses is outside a desired range at a specific time instant within the clock cycle of the clock signal.Type: GrantFiled: September 26, 2014Date of Patent: July 5, 2016Assignee: Infineon Technologies AGInventors: Klemens Kordik, Bernhard Gstoettenbauer, Klaus Buchner, Thomas Sailer
-
Patent number: 9331797Abstract: An RF receiver device includes a semiconductor chip in a chip package, and a test signal generator integrated in the chip. The test signal generator generates an RF test signal including first information. An RF receiver circuit integrated in the chip receives an RF input signal, down-converts the RF input signal into an intermediate frequency (IF) or base band, and digitizes the down-converted signal to obtain a digital signal. An RF receive channel includes a coupler having first and second input ports and an output port. The output port is coupled to the input of the RF receiver circuit, the first input port receives an antenna signal and the second input port receives the test signal from the test signal generator. A signal processor is integrated in the chip and determines, during a test cycle, whether the first information in the digital signal matches a predetermined criterion.Type: GrantFiled: September 23, 2014Date of Patent: May 3, 2016Assignee: Infineon Technologies AGInventors: Klemens Kordik, Rainer Stuhlberger
-
Publication number: 20160094212Abstract: A monitor circuit for monitoring a clock signal is described. In accordance with one example of the disclosure, the monitor circuit includes a pulse generator and a comparator circuit. The pulse generator is configured to generate a sequence of pulses synchronous to the clock signal, wherein each pulse has an edge with a monotonously rising or falling signal level. The comparator circuit receives the sequence of pulses and is configured to detect, for each clock cycle of the clock signal, whether or not the signal level of the sequence of pulses is outside a desired range at a specific time instant within the clock cycle of the clock signal.Type: ApplicationFiled: September 26, 2014Publication date: March 31, 2016Inventors: Klemens Kordik, Bernhard Gstoettenbauer, Klaus Buchner, Thomas Sailer
-
Publication number: 20160087734Abstract: An RF receiver device includes a semiconductor chip in a chip package, and a test signal generator integrated in the chip. The test signal generator generates an RF test signal including first information. An RF receiver circuit integrated in the chip receives an RF input signal, down-converts the RF input signal into an intermediate frequency (IF) or base band, and digitizes the down-converted signal to obtain a digital signal. An RF receive channel includes a coupler having first and second input ports and an output port. The output port is coupled to the input of the RF receiver circuit, the first input port receives an antenna signal and the second input port receives the test signal from the test signal generator. A signal processor is integrated in the chip and determines, during a test cycle, whether the first information in the digital signal matches a predetermined criterion.Type: ApplicationFiled: September 23, 2014Publication date: March 24, 2016Inventors: Klemens Kordik, Rainer Stuhlberger
-
Patent number: 9258000Abstract: A detector for detecting a locked state and an out-of-lock state of a phase locked loop includes an out-of-lock detector circuit that receives a reference signal and an input signal representing a PLL oscillator signal. The out-of-lock detector detects an out-of-lock state of the PLL and generates an out-of-lock signal indicating whether an out-of-lock state is detected. The detector further includes a lock detector circuit that receives the reference signal and the input signal, detects a locked state of the PLL, and generates a lock signal indicating whether a locked state is detected. A logic circuit receives both the out-of-lock signal and the lock signal and combines both signals to obtain an output signal indicative of whether the PLL is in a locked state or an out-of-lock state.Type: GrantFiled: September 23, 2014Date of Patent: February 9, 2016Assignee: Infineon Technologies AGInventors: Klemens Kordik, Thomas Sailer, Rainer Stuhlberger
-
Patent number: 9219487Abstract: An RF transceiver circuit is disclosed herein. In accordance with one example of the disclosure the RF transceiver circuit includes a phase-locked-loop (PLL) with a fractional-N multi-modulus divider. The PLL operates in accordance with a PLL clock frequency and generates a frequency modulated RF output signal. The RF transceiver circuit further includes a modulator unit, which is configured to generate a sequence of division values dependent on a set of modulation parameters. The modulator operates in accordance with a system clock frequency, which is lower than the PLL clock frequency. A sample rate conversion unit is coupled between the modulator unit and a fractional-N multi-modulus divider. The sample rate conversion unit is configured to interpolate the sequence of division ratios to provide an interpolated sequence of division ratios at a rate corresponding to the PLL clock frequency.Type: GrantFiled: August 29, 2014Date of Patent: December 22, 2015Assignee: Infineon Technologies AGInventors: Rainer Stuhlberger, Klemens Kordik
-
Publication number: 20150007002Abstract: A frequency signal generator includes a controllable oscillator unit, a frequency control unit and an error detection unit. The controllable oscillator unit generates and provides a frequency signal. The frequency control unit generates a frequency control signal and the controllable oscillator unit varies a frequency of the frequency signal based on the frequency control signal. Further, the error detection unit receives the frequency control signal, detects an error within the frequency control signal and provides an error signal. The error signal comprises information on a detected error.Type: ApplicationFiled: June 28, 2013Publication date: January 1, 2015Inventors: Bernhard Gstöttenbauer, Klemens Kordik
-
Patent number: 8908748Abstract: An interface circuit includes an interface terminal, a voltage detection device, an output driver and an enable logic. The interface terminal is configured to connect to an interface line. The voltage detection device is configured to detect a voltage present at the interface terminal. The output driver is configured to apply an output signal to the interface terminal. The enable logic is configured to generate an enable signal for the output driver based on an evaluation signal output by the voltage detection device, wherein the enable signal affects an enabling of the output driver if the evaluation signal shows that the voltage present at the interface terminal meets a given condition.Type: GrantFiled: October 15, 2012Date of Patent: December 9, 2014Inventors: Klaus Buchner, Klemens Kordik, Christian Unhold