Patents by Inventor Kmin Hsu

Kmin Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9753895
    Abstract: A method and a corresponding system for process variation analysis of an integrated circuit are provided. A netlist is generated describing electronic devices of an integrated circuit in terms of device parameters and process parameters. The process parameters include local process parameters individual to the electronic devices and global process parameters common to the electronic devices. Critical electronic devices are identified having device parameters with greatest contributions to a performance parameter of a design specification of the integrated circuit. Sensitivity values are determined for the global process parameters and local process parameters of the critical electronic devices. The sensitivity values represent how sensitive the one or more performance parameters are to variations in the global and local process parameters of the critical electronic devices. Monte Carlo (MC) samples are sorted based on the sensitivity values.
    Type: Grant
    Filed: August 5, 2015
    Date of Patent: September 5, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chin-Cheng Kuo, Kmin Hsu, Wei-Yi Hu, Wei Min Chan, Jui-Feng Kuan
  • Patent number: 9519735
    Abstract: In some methods, a number of input data sets is provided for an integrated circuit (IC) model. A number of scores for the number of input data sets, respectively, are then determined based on probabilities of the respective input data sets resulting in a failure condition, which exists when the IC model fails to meet a predetermined yield criteria. A simulation order for the number of input data sets is then assigned according to the determined number of scores.
    Type: Grant
    Filed: September 22, 2014
    Date of Patent: December 13, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chin-Cheng Kuo, Kmin Hsu, Wei-Yi Hu, Wei Min Chan, Jui-Feng Kuan
  • Publication number: 20150339414
    Abstract: A method and a corresponding system for process variation analysis of an integrated circuit are provided. A netlist is generated describing electronic devices of an integrated circuit in terms of device parameters and process parameters. The process parameters include local process parameters individual to the electronic devices and global process parameters common to the electronic devices. Critical electronic devices are identified having device parameters with greatest contributions to a performance parameter of a design specification of the integrated circuit. Sensitivity values are determined for the global process parameters and local process parameters of the critical electronic devices. The sensitivity values represent how sensitive the one or more performance parameters are to variations in the global and local process parameters of the critical electronic devices. Monte Carlo (MC) samples are sorted based on the sensitivity values.
    Type: Application
    Filed: August 5, 2015
    Publication date: November 26, 2015
    Inventors: Chin-Cheng Kuo, Kmin Hsu, Wei-Yi Hu, Wei Min Chan, Jui-Feng Kuan
  • Publication number: 20150089463
    Abstract: In some methods, a number of input data sets is provided for an integrated circuit (IC) model. A number of scores for the number of input data sets, respectively, are then determined based on probabilities of the respective input data sets resulting in a failure condition, which exists when the IC model fails to meet a predetermined yield criteria. A simulation order for the number of input data sets is then assigned according to the determined number of scores.
    Type: Application
    Filed: September 22, 2014
    Publication date: March 26, 2015
    Inventors: Chin-Cheng Kuo, Kmin Hsu, Wei-Yi Hu, Wei Min Chan, Jui-Feng Kuan