Abstract: Bus system (1, 2, 3) for a television signal processing device for transferring video data (d8) of at least one video data source (8) and/or supplementary data (d10) of one or more supplementary-data sources (10) between a transmitter (1) and a receiver (3) by means of a bus (2), wherein at the transmitter end (1), a single data stream (d2) for the bus (2) is formed from the video (d8) and/or supplementary data (d10) by means of an interface circuit (4). The interface circuit (4) combines the video and/or supplementary data, source by source, into blocks (db; db1, db2) following each other successively in time and containing identification data (dk; sk, ik) for start and end, or start and length, and content identification, and transfers the blocks serially.

Abstract: An integrated driver circuit for driving different capacitive loads, which includes a setting element. The setting element develops a setting signal S for a given numerical measure signal M. The numerical measure signal M is developed by an input device, which is coupled to the setting element. The numerical measure signal M corresponds to one of the different capacitive loads which is driven by the driver circuit. Coupled to the setting element is an output stage, which provides an output current that corresponds to the setting signal S.

Abstract: A wavefront array processor where each cell includes a handshake port for asynchronous data transfer with an adjacent cell. The handshake port includes a buffer for receiving data from the adjacent cell and a latch for transferring data to the adjacent cell. Data transfer is accomplished through use of a handshaking protocol which indicates whether or not a receiving buffer is full and if the buffer can receive data. Data can only be transferred if there is room in the buffer to accept the data. The handshaking protocol responds to status signals. A source status signal indicates that a data source has generated a data word. A sink status signal indicates that the buffer can receive data. Each cell further includes a data processing unit, which provides the latch with data and which accesses data from the buffer, and a blocking device, which allows the data processing unit or another handshake port to transfer data to the latch and the buffer to accept data, only when the handshake signals are appropriate.

Abstract: A two-way data transfer device for the data interface between two data-exchanging cells including a data source and a data sink with at least one buffer provided in each cell. When the transmitter buffer is full or the receiver buffer is empty, a backward cell stop signal freezes the state of the data source or the data sink and the cell stop signals are controlled by status signals from the respective buffers.

Abstract: A programmable logic array implemented with complementary insulated-gate field effect transistor technology and formed on a substrate employing a standard AND-OR structure and two non-overlapping clock phases uses diffused capacitors in a dummy row to model the worst case evaluation time of minterms in the AND plane, and a NOR gate, responsive to the dummy row, for enabling the OR plane to sum the minterms generated by the AND plane.