Abstract: In an input/output multiplexer of a data processing unit, a plurality of components, capable of independent activity, provide for the simultaneous execution of a multiplicity of operations involving the exchange of signal groups between a central subsystem and peripheral subsystems. The input/output multiplexer includes apparatus for controlling the receipt from delivery to the central subsystem and peripheral subsystems of signal groups. Apparatus is provided to execute address development normally performed in the central subsystem. Apparatus is also provided to analyze control subsystem signal groups and generate pre-selected command signal groups for delivery to the central subsystem or to the peripheral subsystems. Apparatus in the input/output multiplexer also provides a status of each operation currently in execution.

Abstract: In a data processing unit, apparatus permits more than one central processing unit and associated control interface unit to transfer data to an input/output multiplexer. Thus, more than one central processing unit can have access to a peripheral subsystem. Apparatus is provided which causes the input/output multiplexer to receive sets of data signal groups from the control interface units in sequential order. A signal-free period null signal period is provided by the control unit interface between each set of data signal groups (e.g., each data signal group set includes a single processor sequence). The signal-free period allows the input/output multiplexer to accept waiting data signals from the next sequential control interface unit. Once begun, the transfer of the entire set of data signal groups will proceed without interruption.

Abstract: Priority interrupt apparatus includes a level priority network, a plurality of priority networks, and selector circuits, each corresponding in number to the number of channel sources operative to generate interrupt requests. Each priority network receives requests signals corresponding to different types of possible event signals requiring attention and produces a type code designating the highest priority event from the channel associated therewith. The priority is established in accordance with a preassigned event priority approximating the priorities assignable by program. Each of the selector circuits is connected to receive as a control input the type code signals generated by the priority network associated therewith. Additionally, each selector circuit receives a different set of interrupt level number signals representative of priorities assigned by program to the number of possible event signals.