Patents by Inventor Ko-Chi Chen
Ko-Chi Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11706933Abstract: A semiconductor memory device includes a substrate, a dielectric layer on the substrate, and a contact plug in the dielectric layer. An upper portion of the contact plug protrudes from a top surface of the dielectric layer. The upper portion of the contact plug acts as a first electrode. A buffer layer is disposed on the dielectric layer and beside the upper portion of the contact plug. A resistive-switching layer is disposed beside the buffer layer. A second electrode is disposed beside the resistive-switching layer.Type: GrantFiled: April 7, 2021Date of Patent: July 18, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Wen-Hsin Hsu, Ko-Chi Chen, Tzu-Yun Chang, Chung-Tse Chen
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Patent number: 11508783Abstract: A method for fabricating memory device is provided. The method includes forming a transistor on a substrate. Further, a contact structure is formed on a source/drain region of the transistor. A conductive layer is formed on the contact structure. Four memory structures are formed on the conductive layer to form a quadrilateral structure.Type: GrantFiled: April 20, 2021Date of Patent: November 22, 2022Assignee: UNITED MIICROELECTRONICS CORP.Inventors: Chung-Tse Chen, Ko-Chi Chen, Tzu-Yun Chang
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Publication number: 20220293679Abstract: A semiconductor memory device includes a substrate, a dielectric layer on the substrate, and a contact plug in the dielectric layer. An upper portion of the contact plug protrudes from a top surface of the dielectric layer. The upper portion of the contact plug acts as a first electrode. A buffer layer is disposed on the dielectric layer and beside the upper portion of the contact plug. A resistive-switching layer is disposed beside the buffer layer. A second electrode is disposed beside the resistive-switching layer.Type: ApplicationFiled: April 7, 2021Publication date: September 15, 2022Inventors: Wen-Hsin Hsu, Ko-Chi Chen, Tzu-Yun Chang, Chung-Tse Chen
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Publication number: 20210242282Abstract: A method for fabricating memory device is provided. The method includes forming a transistor on a substrate. Further, a contact structure is formed on a source/drain region of the transistor. A conductive layer is formed on the contact structure. Four memory structures are formed on the conductive layer to form a quadrilateral structure.Type: ApplicationFiled: April 20, 2021Publication date: August 5, 2021Applicant: United Microelectronics Corp.Inventors: Chung-Tse Chen, Ko-Chi Chen, Tzu-Yun Chang
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Patent number: 11024672Abstract: A structure of memory device is provided. The structure of memory device includes a transistor formed on a substrate. A contact structure is disposed on a source/drain region of the transistor. A conductive layer is disposed on the contact structure. Four memory structures is disposed on the conductive layer to form a quadrilateral structure.Type: GrantFiled: May 21, 2019Date of Patent: June 1, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chung-Tse Chen, Ko-Chi Chen, Tzu-Yun Chang
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Publication number: 20200328255Abstract: A structure of memory device is provided. The structure of memory device includes a transistor formed on a substrate. A contact structure is disposed on a source/drain region of the transistor. A conductive layer is disposed on the contact structure. Four memory structures is disposed on the conductive layer to form a quadrilateral structure.Type: ApplicationFiled: May 21, 2019Publication date: October 15, 2020Applicant: United Microelectronics Corp.Inventors: Chung-Tse Chen, Ko-Chi Chen, Tzu-Yun Chang
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Patent number: 10090465Abstract: A semiconductor device is provided, including a lower conducting layer formed above a substrate, an upper conducting layer, and a memory cell structure formed on the lower conducting layer (such as formed between the lower and upper conducting layers). The memory cell structure includes a bottom electrode formed on the lower conducting layer and electrically connected to the lower conducting layer, a transitional metal oxide (TMO) layer formed on the bottom electrode, a TMO sidewall oxides formed at sidewalls of the TMO layer, a top electrode formed on the TMO layer, and spacers formed on the bottom electrode. The upper conducting layer is formed on the top electrode and electrically connected to the top electrode.Type: GrantFiled: November 23, 2016Date of Patent: October 2, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chia-Ching Hsu, Liang Yi, Shen-De Wang, Ko-Chi Chen
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Patent number: 10074692Abstract: A semiconductor structure includes a memory unit structure. The memory unit structure includes a transistor, a first electrode, two second electrode, and two resistive random access memory (RRAM) elements. The first electrode and the two second electrodes are disposed in a horizontal plane. The first electrode is disposed between the two second electrodes. The first electrode and the two second electrodes are disposed in parallel. The first electrode is coupled to a source region of the transistor. One of the two RRAM elements is disposed between the first electrode and one of the two second electrodes. The other one of the two RRAM elements is disposed between the first electrode and the other one of the two second electrodes.Type: GrantFiled: January 31, 2018Date of Patent: September 11, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Wen-Hsin Hsu, Ko-Chi Chen, Tzu-Yun Chang
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Publication number: 20180205013Abstract: A method of forming a Resistive Random Access Memory (RRAM) includes the following steps. A first dielectric layer is formed on a first electrode layer. A second dielectric layer having a first trench is formed on the first dielectric layer. Spacers are formed beside sidewalls of the first trench. Apart of the first dielectric layer exposed by the spacers is removed, thereby forming a second trench in the first dielectric layer. A resistance switching material fills in the second trench. The second dielectric layer and the spacers are removed. A second electrode layer is formed on the resistance switching material and the first dielectric layer. The present invention also provides a RRAM formed by said method.Type: ApplicationFiled: February 24, 2017Publication date: July 19, 2018Inventors: Liang Yi, Chia-Ching Hsu, Shen-De Wang, Ko-Chi Chen
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Publication number: 20180175110Abstract: A semiconductor structure includes a memory unit structure. The memory unit structure includes a transistor, a first electrode, two second electrode, and two resistive random access memory (RRAM) elements. The first electrode and the two second electrodes are disposed in a horizontal plane. The first electrode is disposed between the two second electrodes. The first electrode and the two second electrodes are disposed in parallel. The first electrode is coupled to a source region of the transistor. One of the two RRAM elements is disposed between the first electrode and one of the two second electrodes. The other one of the two RRAM elements is disposed between the first electrode and the other one of the two second electrodes.Type: ApplicationFiled: January 31, 2018Publication date: June 21, 2018Inventors: Wen-Hsin Hsu, Ko-Chi Chen, Tzu-Yun Chang
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Patent number: 9978762Abstract: A method of fabricating a semiconductor device includes providing a substrate with a memory region and a logic region, forming a recess of the substrate in the memory region, forming a non-volatile gate stack in the recess, and forming a logic gate stack in the logic region after forming the non-volatile gate stack.Type: GrantFiled: April 13, 2017Date of Patent: May 22, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chia-Ching Hsu, Ko-Chi Chen, Shen-De Wang
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Patent number: 9966383Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a semiconductor substrate, a non-volatile memory cell, and a gate stack. The non-volatile memory cell is formed in the semiconductor substrate, and a top surface of the non-volatile memory cell is coplanar with or below a top surface of the semiconductor substrate. The gate stack is formed on the semiconductor substrate.Type: GrantFiled: November 24, 2015Date of Patent: May 8, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Liang Yi, Ko-Chi Chen, Shen-De Wang
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Publication number: 20180108837Abstract: A semiconductor device is provided, including a lower conducting layer formed above a substrate, an upper conducting layer, and a memory cell structure formed on the lower conducting layer (such as formed between the lower and upper conducting layers). The memory cell structure includes a bottom electrode formed on the lower conducting layer and electrically connected to the lower conducting layer, a transitional metal oxide (TMO) layer formed on the bottom electrode, a TMO sidewall oxides formed at sidewalls of the TMO layer, a top electrode formed on the TMO layer, and spacers formed on the bottom electrode. The upper conducting layer is formed on the top electrode and electrically connected to the top electrode.Type: ApplicationFiled: November 23, 2016Publication date: April 19, 2018Inventors: Chia-Ching Hsu, Liang Yi, Shen-De Wang, Ko-Chi Chen
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Patent number: 9923028Abstract: A semiconductor structure includes a memory unit structure. The memory unit structure includes a transistor, a first electrode, two second electrode, and two resistive random access memory (RRAM) elements. The first electrode and the two second electrodes are disposed in a horizontal plane. The first electrode is disposed between the two second electrodes. The first electrode and the two second electrodes are disposed in parallel. The first electrode is coupled to a source region of the transistor. One of the two RRAM elements is disposed between the first electrode and one of the two second electrodes. The other one of the two RRAM elements is disposed between the first electrode and the other one of the two second electrodes.Type: GrantFiled: January 10, 2017Date of Patent: March 20, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Wen-Hsin Hsu, Ko-Chi Chen, Tzu-Yun Chang
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Publication number: 20180033961Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a bottom metal layer, a resistive random access memory (ReRAM) cell structure, and an upper metal layer. The bottom metal layer is located above the substrate. The ReRAM cell structure is formed on the bottom metal layer. The ReRAM cell structure includes a bottom electrode, a memory cell layer, a top electrode, and a spacer. The memory cell layer is formed on the bottom electrode. The top electrode is formed on the memory cell layer. The spacer is formed on two sides of the bottom electrode, the memory cell layer and the top electrode. The upper metal layer is electrically connected to and directly contacting the top electrode.Type: ApplicationFiled: September 9, 2016Publication date: February 1, 2018Inventors: Liang Yi, Chia-Ching Hsu, Shen-De Wang, Ko-Chi Chen
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Patent number: 9859335Abstract: A semiconductor device includes an interconnection formed above a substrate, and the interconnection comprising interconnect layers respectively buried in dielectric layers; a lower conducting layer formed above the substrate; a memory cell structure formed on the lower conducting layer and buried in one of the dielectric layers; an upper conducting layer formed on the memory cell structure. The memory cell structure includes a bottom electrode formed on and electrically connected to the lower conducting layer; a transitional metal oxide (TMO) layer formed on the bottom electrode; and a top electrode formed on the TMO layer, wherein the upper conducting layer is formed on the top electrode and electrically connected to the top electrode. Also, the lower conducting layer and the upper conducting layer are positioned in the different dielectric layers.Type: GrantFiled: December 2, 2016Date of Patent: January 2, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chia-Ching Hsu, Liang Yi, Shen-De Wang, Ko-Chi Chen
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Patent number: 9806255Abstract: A resistive random access memory includes a lower electrode, an upper electrode and a resistive layer between the lower electrode and the upper electrode, wherein the resistive layer includes a constant-resistance portion and a variable-resistance portion surrounding the constant-resistance portion.Type: GrantFiled: March 10, 2017Date of Patent: October 31, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chia-Ching Hsu, Liang Yi, Shen-De Wang, Ko-Chi Chen
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Patent number: 9799705Abstract: The present invention provides a semiconductor device. The semiconductor device includes a contact structure disposed in a first dielectric layer, a second dielectric layer disposed on the first dielectric layer and having an opening disposed therein, a spacer disposed in the opening and partially covering the contact structure, and a resistive random-access memory (RRAM) disposed on the contact structure and directly contacting the spacer, wherein the RRAM includes a bottom electrode, a top electrode, and a switching resistance layer disposed between the bottom electrode and the top electrode.Type: GrantFiled: October 19, 2016Date of Patent: October 24, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Liang Yi, Chia-Ching Hsu, Shen-De Wang, Ko-Chi Chen, Guoan Du
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Patent number: 9761680Abstract: The present invention provides a semiconductor device, including a substrate with a memory region and a logic region, the substrate having a recess disposed in the memory region, a logic gate stack disposed in the logic region, and a non-volatile memory disposed in the recess. The non-volatile memory includes at least two floating gates and at least two control gates disposed on the floating gates, where each floating gate has a step-shaped bottom, and the step-shaped bottom includes a first bottom surface and a second bottom surface lower than the first bottom surface.Type: GrantFiled: October 26, 2015Date of Patent: September 12, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Dongdong Li, Ko-Chi Chen, Shen-De Wang
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Publication number: 20170221913Abstract: A method of fabricating a semiconductor device includes providing a substrate with a memory region and a logic region, forming a recess of the substrate in the memory region, forming a non-volatile gate stack in the recess, and forming a logic gate stack in the logic region after forming the non-volatile gate stack.Type: ApplicationFiled: April 13, 2017Publication date: August 3, 2017Inventors: Chia-Ching Hsu, Ko-Chi Chen, Shen-De Wang