Abstract: Some embodiments of the present disclosure relate to an integrated chip including an extended via that spans a combined height of a wire and a via and that has a smaller footprint than the wire. The extended via may replace a wire and an adjoining via at locations where the sizing and the spacing of the wire are reaching lower limits. Because the extended via has a smaller footprint than the wire, replacing the wire and the adjoining via with the extended via relaxes spacing and allows the size of the pixel to be further reduced. The extended via finds application for capacitor arrays used for pixel circuits.

Abstract: A system, method and computer program product are disclosed that enable providing processing instructions for updating schema. In one embodiment, the method includes obtaining an updated schema that includes an updated version of a previous schema; identifying a difference between the updated schema and the previous schema; processing the difference to create processing instructions; and providing the processing instructions for implementation into a logical processor, wherein the logical processor processes data defined using the updated schema.

Abstract: A system, method and computer program product are disclosed that enable providing processing instructions for updating schema. In one embodiment, the method includes obtaining an updated schema that includes an updated version of a previous schema; identifying a difference between the updated schema and the previous schema; processing the difference to create processing instructions; and providing the processing instructions for implementation into a logical processor, wherein the logical processor processes data defined using the updated schema.