Abstract: A semiconductor die includes an on-die power switch and a target device. The on-die power switch includes a plurality of power input nodes, a power output node, and a switch circuit. The power input nodes receive a plurality of operation voltages from a plurality of different power sources, respectively. The power output node outputs a target operation voltage selected from the operation voltages. The switch circuit selectively couples one of the power input nodes to the power output node. The target device operates according to the target operation voltage supplied from the on-die power switch. The on-die power switch and the target device are separate circuit blocks of the semiconductor die.

Abstract: A multi-chip system includes a plurality of chips and a monitoring and calibration system. The plurality of chips include at least a first chip and a second chip, wherein an output port of the first chip is connected to an input port of the second chip via a chip-to-chip connection, the first chip transmits an output signal to the second chip via the chip-to-chip connection, and the second chip processes an input signal that is derived from the output signal transmitted via the chip-to-chip connection. The monitoring and calibration system calibrates a chip setting of at least one of the first chip and the second chip for pulse width calibration of the input signal.

Abstract: A multi-chip system includes a plurality of chips and a monitoring and calibration system. The plurality of chips include at least a first chip and a second chip, wherein an output port of the first chip is connected to an input port of the second chip via a chip-to-chip connection, the first chip transmits an output signal to the second chip via the chip-to-chip connection, and the second chip processes an input signal that is derived from the output signal transmitted via the chip-to-chip connection. The monitoring and calibration system calibrates a chip setting of at least one of the first chip and the second chip for pulse width calibration of the input signal.

Abstract: The present invention discloses a charge control circuit for supplying power from an external power source to a first common node and charging a second common node from the first common node. A regulator circuit is coupled between the external power source and the first common node, and a transistor is coupled between the first common node and the second common node. The present invention detects an operation parameter of the transistor and controls an internal voltage source to generate a non-predetermined voltage difference accordingly. When the sum of the voltage at the second common node and the non-predetermined voltage is equal to or higher than the reference voltage, the voltage at the first common node is regulated to a level higher than the voltage at the second common node, and the transistor is in an optimum conductive state.

Abstract: The present invention discloses a charge control circuit for supplying power from an external power source to a first common node and charging a second common node from the first common node. A regulator circuit is coupled between the external power source and the first common node, and a transistor is coupled between the first common node and the second common node. The present invention detects an operation parameter of the transistor and controls an internal voltage source to generate a non-predetermined voltage difference accordingly. When the sum of the voltage at the second common node and the non-predetermined voltage is equal to or higher than the reference voltage, the voltage at the first common node is regulated to a level higher than the voltage at the second common node, and the transistor is in an optimum conductive state.

Abstract: The image sticking erasing circuit includes a detection circuit and a switching circuit connected to the detection circuit. The detection circuit is for use in detecting a first voltage signal, which closely follows the variation of the voltage source, and a reference voltage, which loosely follows the variation of the voltage source. When the detection circuit determines that the first voltage signal is lower than a first threshold value, the switching circuit switches the gate of a driving transistor to a second voltage signal, which loosely follows the voltage source. When the detection circuit determines that the reference voltage signal is lower than a second threshold value, the switching circuit switches the gate of a driving transistor to a low voltage state.