Abstract: Some embodiments relate to an integrated device, including a first contact wire comprising an upper surface over a substrate; a plurality of shielding wires level with the first contact wire and having upper surfaces that are level with the upper surface of the first contact wire; and a first capacitor having an upper layer and a plurality of protrusions including a first protrusion and a second protrusion extending from the upper layer in a first direction towards the shielding wires; wherein the first protrusion extends to the upper surface of the first contact wire; and wherein the second protrusion is over and separated from the shielding wires in the first direction.

Abstract: Some embodiments relate to a method that includes depositing a first layer of hard mask material over a layer of dielectric material; etching the first layer of the hard mask material, the etched first layer of hard mask material including an etched portion having a first lateral dimension; depositing a second layer of the hard mask material over the first layer of the hard mask material; etching at least a portion of the second layer of the hard mask material, while allowing a remaining portion of the hard mask material, to expose a portion of the layer of the dielectric material that has a second lateral dimension less than the first lateral dimension; and etching a trench into the layer of the dielectric material at the exposed portion of the layer of the dielectric material.

Abstract: An embodiment high-density capacitor includes a bottom electrode having a plurality of non-concentric cylindrical portions, a top electrode including a plurality of vertical portions and a surrounding portion, and a dielectric layer separating the top electrode from the bottom electrode. Each of the plurality of non-concentric cylindrical portions includes an inner shell and an outer shell and each of the plurality of vertical portions is vertically surrounded by the inner shell of a respective cylindrical portion of the bottom electrode. The surrounding portion of the top electrode respectively vertically surrounds each of the plurality of non-concentric cylindrical portions of the bottom electrode such that adjacent non-concentric cylindrical portions of the bottom electrode are separated from one another by the surrounding portion of the top electrode. At least some of the plurality of non-concentric cylindrical portions of the bottom electrode include a spatial distribution having a hexagonal symmetry.

Abstract: Some embodiments of the present disclosure relate to an integrated chip including an extended via that spans a combined height of a wire and a via and that has a smaller footprint than the wire. The extended via may replace a wire and an adjoining via at locations where the sizing and the spacing of the wire are reaching lower limits. Because the extended via has a smaller footprint than the wire, replacing the wire and the adjoining via with the extended via relaxes spacing and allows the size of the pixel to be further reduced. The extended via finds application for capacitor arrays used for pixel circuits.