Abstract: The stacked semiconductor device includes a semiconductor substrate, a multi-layered insulation layer pattern having at least two insulation layer patterns and an opening, an active layer pattern formed on each of the insulation layer patterns, a first plug including single crystalline silicon-germanium, a second plug including single crystalline silicon, and a wiring electrically connected to the first plug and sufficiently filling up the opening. The insulation layer patterns are vertically stacked on the semiconductor substrate and the opening exposes an upper face of the semiconductor substrate. A side portion of the active layer pattern is exposed by the opening. The first plug is formed on the upper face of the semiconductor substrate to partially fill the opening. The second plug is partially formed on the first plug, and has substantially the same interface as that of the first plug.

Abstract: The stacked semiconductor device includes a semiconductor substrate, a multi-layered insulation layer pattern having at least two insulation layer patterns and an opening, an active layer pattern formed on each of the insulation layer patterns, a first plug including single crystalline silicon-germanium, a second plug including single crystalline silicon, and a wiring electrically connected to the first plug and sufficiently filling up the opening. The insulation layer patterns are vertically stacked on the semiconductor substrate and the opening exposes an upper face of the semiconductor substrate. A side portion of the active layer pattern is exposed by the opening. The first plug is formed on the upper face of the semiconductor substrate to partially fill the opening. The second plug is partially formed on the first plug, and has substantially the same interface as that of the first plug.

Abstract: In a method of forming a layer having a lower electrical resistance and a method of manufacturing a semiconductor device, a first layer may be formed on a single crystalline substrate using amorphous silicon doped with impurities. A heat treatment may be performed on the single crystalline substrate at a temperature of about 550° C. to about 600° C. to convert the first layer into a second layer including a single crystalline silicon film transformed from a lower portion of the first layer contacting the single crystalline substrate and a polysilicon film transformed from an upper portion of the first layer. The layer may be formed at a relatively low temperature by a selective epitaxial growth process, and thus degradation or damage to a semiconductor device, which may be generated in a high temperature process, may be reduced.

Abstract: In a capacitor having a semiconductor-insulator-metal (SIM) structure, an upper electrode may be formed into a multilayer structure including a polycrystalline semiconductor Group IV material. A dielectric layer may include a metal oxide, and a lower electrode may include a metal-based material. Therefore, a capacitor may have a sufficiently small equivalent oxide thickness (EOT) and/or may have improved current leakage characteristics.