Abstract: The present invention provides an audio recording method and an associated audio processing circuit. The recording method includes performing an initialization of an audio processing circuit at a first timing, setting a gain of the audio processing circuit to a first value at a second timing, using the audio processing circuit to start recording at a third timing, completing the initialization of the audio processing circuit at a fourth timing, and adjusting the gain of the audio processing circuit to a second value at a fifth timing. The second value is greater than the first value, the first timing and the second timing are earlier than the third timing, the fourth timing is later than the third timing, and the fifth timing is later than the third timing.

Abstract: An embedded device including a random access memory (RAM) and a processor is provided. The processor includes a processor core and an authentication module. The RAM stores data-to-be-authenticated. The data includes a program code to be executed by the processor core. The authentication module periodically accesses and authenticates the data-to-be-authenticated in the RAM. When the authentication module deems that the program code in the RAM loses its integrity, the authentication module interrupts the processor from further executing the program code.

Abstract: A memory access authority control method and a memory management system utilizing the method. By partitioning and designating permissible memory access intervals to different service programs in one system, it is ensured that each service program cannot access other service programs' confidential data. Thus, the security of confidential data is guaranteed.

Abstract: A memory access authority control method and a memory management system utilizing the method. By partitioning and designating permissible memory access intervals to different service programs in one system, it is ensured that each service program cannot access other service programs' confidential data. Thus, the security of confidential data is guaranteed.

Abstract: An accumulating operator is applicable to a digital data processor to realize an output floating point number in response to a first floating point number and a second floating point number. The accumulating operator comprises a splitter dividing the first floating point number into a third floating point number and a compensation number, wherein an exponent of the third floating point number is equal to or greater than the exponent of the second floating point number; an accumulator electrically connected to the splitter for operating the second and third floating point numbers to realize a fourth floating point number; and a compensator electrically connected to the splitter and the accumulator for operating the fourth floating point number and the compensation number to realize the output floating point number. Via compensation, the precision of the floating point operation can be improved.

Abstract: Power management methods and systems. First, a running cycle of a processing unit processing a data unit is recorded. A gating signal is generated according to the running cycle and a performance requirement, and a working clock is adjusted according to the gating signal. Thereafter, the adjusted working signal is provided to the processing unit.

Abstract: A vertex shader. The vertex shader comprises an instruction register file, a flow controller, a thread arbitrator, and an arithmetic logic unit (ALU) pipe. The instruction register file stores a plurality of instructions. The flow controller concurrently executing a plurality of threads, reads the instructions in order from the instruction register file for the threads and accesses vertex data for the threads. The thread arbitrator checks the dependency of instructions in the threads and selects the thread to execute in accordance with the result of the dependency check and a thread execution priority. The arithmetic logic unit (ALU) pipe receives the vertex data for executing the instructions of the thread selected by the thread arbitrator for three-dimensional (3D) graphics computations.

Abstract: A logic unit is provided for performing operations in multiple threads on vertex data. The logic unit comprises a macro instruction register file, a flow control instruction register file, and a flow controller. The macro instruction register file stores macro blocks with each macro block including at least one instruction. The flow control instruction register file stores flow control instructions with each flow control instruction including at least one called macro block and dependency information of the called macro block.

Abstract: Power management methods and systems. First, a running cycle of a processing unit processing a data unit is recorded. A gating signal is generated according to the running cycle and a performance requirement, and a working clock is adjusted according to the gating signal. Thereafter, the adjusted working signal is provided to the processing unit.

Abstract: The texture engine, provided in this disclosure, comprises a texel location calculator, a texture cache unit, and a video processing unit. The texel location calculator receives a texture and video request for a pixel, including location information of texture data for the pixel in a texture map stored in a memory unit and information of video processing required for the pixel. The texel location calculator computes memory addresses of the texture data in the memory unit and graphics data required for the pixel when performing the video processing specified in the texture and video request in the memory unit. The texture cache unit retrieves a copy of the graphics data and texture data from the memory unit with the memory addresses computed by the texel location calculator. The video processing unit receives the graphics data to perform the video processing specified in the texture and video request on the graphics data.

Abstract: A X-Y plane is divided into a plurality of tile rows. Each tile row covered by a triangle to be processed includes one or more tiles. The tiles in the same tile row are rastered in a specified order.

Abstract: An accumulating operator is applicable to a digital data processor to realize an output floating point number in response to a first floating point number and a second floating point number. The accumulating operator comprises a splitter dividing the first floating point number into a third floating point number and a compensation number, wherein an exponent of the third floating point number is equal to or greater than the exponent of the second floating point number; an accumulator electrically connected to the splitter for operating the second and third floating point numbers to realize a fourth floating point number; and a compensator electrically connected to the splitter and the accumulator for operating the fourth floating point number and the compensation number to realize the output floating point number. Via compensation, the precision of the floating point operation can be improved.

Abstract: The present invention proposes a multimedia-instruction acceleration device for increasing efficiency and a method for the same, which uses instruction strings having a floating-point value check field to execute commands of single-instruction/multi-data format, and further transforms the floating-point value to a fixed one. The present invention can effectively save executing time and simplify numerical calculation process, and can fully exploit memory space to achieve the object of increasing acceleration operation and execution of multimedia instructions.

Abstract: A system and method for clearing buffer for three-dimensional rendering is disclosed, which is used in a multimedia chip. The multimedia chip is used for controlling the three-dimensional rendering and accessing a memory, and the memory includes a buffer for storing depth data of a number of pixels during three-dimensional rendering. In addition, the multimedia chip includes a multimedia related circuit. The system includes a memory interface controller and a Z clearing controller. The memory interface controller is used for receiving a conventional command signal from the multimedia related circuit, and for detecting state of the memory. The Z clearing controller is employed for receiving X- and Y-coordinates of a pixel that the multimedia related circuit is to draw, and for sending a command signal to the memory interface controller, wherein the Z clearing controller performs Z clearing on the buffer when the memory is in an idle state.