Abstract: A read-only memory structure and method of manufacture comprising the steps of sequentially forming a tunneling oxide layer, a first polysilicon layer, a bottom oxide layer and a silicon nitride layer over a semiconductor substrate having field oxide layers already formed thereon. A mask is used to pattern the various layers above the semiconductor substrate forming a floating gate out of the first polysilicon layer. Thereafter, a doped region in formed in the semiconductor substrate, and then a chemical vapor deposition method is used to form a top oxide layer and a second silicon nitride layer over the first silicon nitride layer. Subsequently, the second silicon nitride layer is etched back to form spacers on the sidewalls of the floating gate. Next, thermal oxidation is carried out so that the doped region is oxidized into an etching barrier layer while a silicon oxy-nitride layer is formed over the surface of the spacers. Thereafter, an annealing operation is performed to densify the oxide layer.