Patents by Inventor Ko IMAOKA
Ko IMAOKA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10680068Abstract: A technique related to a bonded semiconductor substrate capable of reducing an interface resistance is provided. The semiconductor substrate comprises a single-crystalline SiC substrate and a polycrystalline SiC substrate. The single-crystalline SIC substrate and the polycrystalline SiC substrate are bonded. A bonded region of the single-crystalline SiC substrate and the polycrystalline SiC substrate contains 1×1021 (atoms/cm3) or more of particular atoms.Type: GrantFiled: July 13, 2017Date of Patent: June 9, 2020Assignee: SICOXS CORPORATIONInventors: Ko Imaoka, Takanori Murasaki, Toshihisa Shimo, Hidetsugu Uchida, Akiyuki Minami
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Publication number: 20200006493Abstract: A technique related to a bonded semiconductor substrate capable of reducing an interface resistance is provided. The semiconductor substrate comprises a single-crystalline SiC substrate and a polycrystalline SiC substrate. The single-crystalline SIC substrate and the polycrystalline SiC substrate are bonded. A bonded region of the single-crystalline SiC substrate and the polycrystalline SiC substrate contains 1×1021 (atoms/cm3) or more of particular atoms.Type: ApplicationFiled: July 13, 2017Publication date: January 2, 2020Applicant: SICOXS CORPORATIONInventors: Ko IMAOKA, Takanori MURASAKI, Toshihisa SHIMO, Hidetsugu UCHIDA, Akiyuki MINAMI
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Patent number: 9773678Abstract: A method for manufacturing a semiconductor substrate may comprise irradiating a surface of a first semiconductor layer and a surface of a second semiconductor layer with one or more types of first impurity in a vacuum. The method may comprise bonding the surface of the first semiconductor layer and the surface of the second semiconductor layer to each other in the vacuum. The method may comprise applying heat treatment to the semiconductor substrate produced in the bonding. The first impurity may be an inert impurity that does not generate carriers in the first and second semiconductor layers. The heat treatment may be applied such that a width of an in-depth concentration profile of the first impurity contained in the first and second semiconductor layers is narrower after execution of the heat treatment than before the execution of the heat treatment.Type: GrantFiled: July 9, 2015Date of Patent: September 26, 2017Assignees: KABUSHIKI KAISHA TOYOTA JIDOSHOKKI, SICOXS CORPORATIONInventors: Ko Imaoka, Motoki Kobayashi, Hidetsugu Uchida, Kuniaki Yagi, Takamitsu Kawahara, Naoki Hatta, Akiyuki Minami, Toyokazu Sakata, Tomoatsu Makino, Mitsuharu Kato
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Patent number: 9761479Abstract: A technique disclosed herein relates to a manufacturing method for a semiconductor substrate having the bonded interface with high bonding strength without forming an oxide layer at the bonded interface also for the substrate having surface that is hardly planarized. The manufacturing method for the semiconductor substrate may include an amorphous layer formation process in which a first amorphous layer is formed by modifying a surface of a support substrate and a second amorphous layer is formed by modifying a surface of a single-crystalline layer of a semiconductor. The manufacturing method may include a contact process in which the first amorphous layer and the second amorphous layer are contacted with each other. The manufacturing method may include a heat treatment process in which the support substrate and single-crystalline layer are heat-treated with the first amorphous layer and the second amorphous layer being in contact with each other.Type: GrantFiled: July 3, 2014Date of Patent: September 12, 2017Assignees: KABUSHIKI KAISHA TOYOTA JIDOSHOKKI, SICOXS CORPORATION, NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGYInventors: Ko Imaoka, Motoki Kobayashi, Hidetsugu Uchida, Kuniaki Yagi, Takamitsu Kawahara, Naoki Hatta, Akiyuki Minami, Toyokazu Sakata, Tomoatsu Makino, Hideki Takagi, Yuuichi Kurashima
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Publication number: 20170213735Abstract: A method for manufacturing a semiconductor substrate may comprise irradiating a surface of a first semiconductor layer and a surface of a second semiconductor layer with one or more types of first impurity in a vacuum. The method may comprise bonding the surface of the first semiconductor layer and the surface of the second semiconductor layer to each other in the vacuum. The method may comprise applying heat treatment to the semiconductor substrate produced in the bonding. The first impurity may be an inert impurity that does not generate carriers in the first and second semiconductor layers. The heat treatment may be applied such that a width of an in-depth concentration profile of the first impurity contained in the first and second semiconductor layers is narrower after execution of the heat treatment than before the execution of the heat treatment.Type: ApplicationFiled: July 9, 2015Publication date: July 27, 2017Applicants: KABUSHIKI KAISHA TOYOTA JIDOSHOKKI, SICOXS CORPORATIONInventors: Ko IMAOKA, Motoki KOBAYASHI, Hidetsugu UCHIDA, Kuniaki YAGI, Takamitsu KAWAHARA, Naoki HATTA, Akiyuki MINAMI, Toyokazu SAKATA, Tomoatsu MAKINO, Mitsuharu KATO
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Publication number: 20160322219Abstract: A semiconductor substrate including plural types of semiconductor layers exposed at a surface thereof is provided. A semiconductor substrate includes: a supporting substrate; a single-crystal, first semiconductor layer disposed on a surface of the supporting substrate; a single-crystal, second semiconductor layer disposed on parts of a surface of the first semiconductor layer; and a single-crystal, third semiconductor layer disposed on those parts of the surface of the first semiconductor layer on which the second semiconductor layer is not disposed. The third semiconductor layer has a crystal orientation aligned with that of the first semiconductor layer and is made of the same material as the first semiconductor layer.Type: ApplicationFiled: December 25, 2014Publication date: November 3, 2016Inventors: Ko IMAOKA, Hidetsugu UCHIDA, Jun SUDA
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Publication number: 20160204023Abstract: A technique disclosed herein relates to a manufacturing method for a semiconductor substrate having the bonded interface with high bonding strength without forming an oxide layer at the bonded interface also for the substrate having surface that is hardly planarized. The manufacturing method for the semiconductor substrate may include an amorphous layer formation process in which a first amorphous layer is formed by modifying a surface of a support substrate and a second amorphous layer is formed by modifying a surface of a single-crystalline layer of a semiconductor. The manufacturing method may include a contact process in which the first amorphous layer and the second amorphous layer are contacted with each other. The manufacturing method may include a heat treatment process in which the support substrate and single-crystalline layer are heat-treated with the first amorphous layer and the second amorphous layer being in contact with each other.Type: ApplicationFiled: July 3, 2014Publication date: July 14, 2016Applicants: KABUSHIKI KAISHA TOYOTA JIDOSHOKKI, SICOXS CORPORATION, NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGYInventors: Ko IMAOKA, Motoki KOBAYASHI, Hidetsugu UCHIDA, Kuniaki YAGI, Takamitsu KAWAHARA, Naoki HATTA, Akiyuki MINAMI, Toyokazu SAKATA, Tomoatsu MAKINO, Hideki TAKAGI, Yuuichi KURASHIMA
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Publication number: 20150069996Abstract: An optical fiber for a sensor that can measure a current or a voltage precisely is provided. The optical fiber for the sensor 10 comprises: an FBG 12 wherein a refractive index of a core changes periodically; a metal layer 13 for sheathing the FBG 12; and a pair of electrodes 14 and 15 provided at the metal layer 13. The electrodes 14 and 15 are connected to an object to be measured in desired positions. Current flowing through the metal layer 13 is calculated based on variation in Bragg wavelength of the FBG 12.Type: ApplicationFiled: January 21, 2013Publication date: March 12, 2015Applicants: KABUSHIKI KAISHA TOYOTA JIDOSHOKKI, INSTITUTE OF NATIONAL COLLEGES OF TECH, JAPAN, NATIONAL UNIVERSITY CORPORATION KAGAWA UNIVERSITYInventors: Ko Imaoka, Yoshifumi Suzaki, Hiromu Iwata, Kiyoshi Nakagawa
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Publication number: 20150023389Abstract: An optical fiber for a temperature sensor and a power device monitoring system that can measure temperatures at different measurement positions by a simple construction are provided. An optical fiber for the sensor 10 comprises a temperature assurance FBG 20 and temperature measurement FBGs 30 as FBGs wherein the refractive index of a core changes periodically. Wavelength band of light incident to the optical fiber for the sensor 10 includes Bragg wavelengths of the temperature assurance FBG 20 and the temperature measurement FBGs 30. The power device monitoring system 1 measures temperatures of the temperature assurance FBG 20 and the temperature measurement FBGs 30 based on their Bragg wavelengths.Type: ApplicationFiled: January 21, 2013Publication date: January 22, 2015Applicants: KABUSHIKI KAISHA TOYOTA JIDOSHOKKI, NATIONAL UNIVERSITY CORPORATION KAGAWA UNIVERSITY, INSTITUTE OF NATIONAL COLLEGES OF TECHNOLOGY, JAPANInventors: Ko Imaoka, Yoshifumi Suzaki, Hiromu Iwata, Kiyoshi Nakagawa
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Publication number: 20110280768Abstract: An ammonia supply device includes an ammonia absorber, a conductive element, a mixture, a tank and an electrode. The ammonia absorber is in powder or granular form. Ammonia is stored in the ammonia absorber and released from the ammonia absorber. The conductive element in paste or liquid form has a conductive property and a nonreactive property with ammonia. The mixture is made by mixing the ammonia absorber and the conductive element. The tank holds the mixture. The electrode includes a pair of first and second electrode elements for applying voltage to the mixture.Type: ApplicationFiled: May 5, 2011Publication date: November 17, 2011Applicant: KABUSHIKI KAISHA TOYOTA JIDOSHOKKIInventors: Shintaro KAWASAKI, Ko IMAOKA