Abstract: An operating system (OS) includes a kernel, and a hardware (HW) interrupt processing unit capable of processing arrival of data from an interface unit in a polling mode or an interrupt mode, and an on-server data transmission controller includes: a packet arrival monitoring unit that starts up a thread that monitors arrival of a packet using a polling model in the kernel; and a transmission processing unit that, when the packet arrival monitoring unit detects the arrival of the packet, notifies a protocol processing unit in an application of presence of an arriving packet without using a kernel protocol stack.

Abstract: An accelerator offload device that offloads specific processing of an application to an accelerator includes: a request-related processing part that performs predetermined processing required before performing offloading to the accelerator and then notifies a request I/O part of a request to perform offloading; the request I/O part, which operates on a first CPU core and which notifies the accelerator of an offload request; a response I/O part which operates on a second CPU core different from the first CPU core and which notifies a response-related processing part of operation completion of the accelerator; the response-related processing part, which performs an operation described in the application by using an operation result of the accelerator; and an interrupt destination control part that sets an interrupt destination CPU core to which the accelerator is to raise an interrupt and which is to be used as the second CPU core.

Abstract: A server delay controller includes: a packet harvesting unit that refers to a packet held in a ring buffer when a packet arrives and executes harvesting to delete an entry of a corresponding queue from the ring buffer, a sleep management unit that puts the thread to sleep in a case in which a packet does not arrive for a predetermined period, and cancels the sleep of the thread through a hardware interrupt at the time of packet arrival, and an idle state recovery control unit that periodically wakes up the thread during sleep or wakes up the thread immediately before the packet arrival in accordance with a packet arrival timing.

Abstract: An accelerator state control device includes a plurality of accelerators having different processing performance, and controls a state of the accelerators when arithmetic processing is performed by offloading specific processing of an application to the accelerators. The accelerator state control device includes: when data in which different processing deadlines are mixed is input, an arithmetic device performance collection/recording unit that collects and records performance information of the accelerators; a traffic amount/processing deadline prediction unit that predicts a traffic amount and a processing deadline; and an arithmetic device allocation determination unit that obtains a data amount corresponding to the processing deadline, and determines an accelerator that satisfies the performance on the basis of the data amount.

Abstract: A signal processing resource switching device includes a function proxy execution unit configured to accept a “function name?argument” from an application unit and notify the application of argument data of a function when the function is executed or ended by a calculation resource, an accelerator failure detection unit configured to detect a failure of an accelerator, and an offload destination calculation resource determination unit configured to determine an unfailed and available resource among the calculation resources, and the function proxy execution unit performs offloading on the resource determined by the offload destination calculation resource determination unit.

Abstract: A server delay controller includes: a sleep management unit that makes a thread sleep when no packet arrives for a predetermined period and cancels the sleep of the thread with a hardware interrupt when the packet arrives; a HW interrupt frequency management table that stores the number of times of hardware interrupt; and a HW interrupt frequency control unit that calculates a HW interrupt frequency on the basis of the number of times of hardware interrupt and controls HW interrupt permission or prohibition by sleep of the sleep management unit on the basis of the calculated HW interrupt frequency.

Abstract: An accelerator offload device (100) includes: a data processing amount acquisition part (110) that acquires a data processing amount that is a data processing amount at the current time of offload target processing being performed and/or a predicted data processing amount; an operation destination determination part (120) that determines whether to perform an operation by a CPU (11) or offload the operation to an ACC (12) based on the data processing amount of an APL (1), and when a change is necessary, changes an offload destination of an operation processing offload part (130); and an operation processing offload part (130) that receives a request of operation processing from the APL (1), stores data to be processed and a processing instruction in a shared memory, and causes the CPU (11) or the ACC (12) to execute pertinent processing.

Abstract: A server delay control device that is set up in a kernel space of an OS and started as a thread to use a polling model to monitor an arriving packet, wherein the thread has operation modes of a sleep control mode in which the thread is put to sleep and a constantly busy poll mode in which the thread is kept constantly busy polling, and the server delay control device includes a traffic frequency measurement unit that measures traffic inflow frequency, and a mode switching control unit that switches an operation mode of the thread between the sleep control mode and the constantly busy poll mode, on the basis of the traffic inflow frequency measured by the traffic frequency measurement unit.

Abstract: A server delay controller includes: a packet harvesting unit that refers to a packet held in a ring buffer when a packet arrives and executes harvesting to delete an entry of a corresponding queue from the ring buffer, a sleep management unit that puts the thread to sleep in a case in which a packet does not arrive for a predetermined period, and cancels the sleep of the thread through a hardware interrupt at the time of packet arrival, and an idle state recovery control unit that periodically wakes up the thread during sleep or wakes up the thread immediately before the packet arrival in accordance with a packet arrival timing.

Abstract: A base station switching controller is a power saving base station switching device that switches a base station that processes a wireless access signal, and the base station switching controller includes: a base station optimum allocation/switching determiner that selects one of suitable base stations from a base station pool in which a plurality of base stations having different characteristics according to predetermined requirements are pooled and arranged in advance on the basis of traffic information collected by a traffic information collector; and a network switching controller that switches a network between a network to be connected to a switching source base station and a network to be connected to a switching destination base station.

Abstract: A server (200) includes a userland APL (230) that cooperates with an accelerator (212) while bypassing an OS (220). The userland APL (230) includes an ACC-NIC common data parsing part (232) that parses reception data in which an input data format of an ACC utilizing function and an NIC reception data format are made common.

Abstract: An accelerator offload device that offloads specific processing of an application program to an accelerator includes: a request-related processing part; a request I/O part; a response I/O part; and a response-related processing part. The request-related processing part is configured to perform predetermined processing required before performing offloading to the accelerator and then notify the request I/O part of a request to perform offloading. The request I/O part is configured to operate on a first CPU core to perform request processing of notifying the accelerator of an offload request. The response I/O part is configured to operate on a second CPU core different from the first CPU core to perform response processing of notifying the response-related processing part of operation completion of the accelerator. The response-related processing part is configured to perform an operation described in the application program by using an operation result of the accelerator.

Abstract: A resource scheduling unit of a base station 100 assigns an RE multiplexed in a time domain and a frequency domain to each UE. The resource scheduling unit includes the following: a resource assignment calculation unit that performs scheduling of assigning a resource by assigning the resource to one side of a time axis in a case where traffic between the UE and the base station is equal to or less than a predetermined value; and a sleep control unit that distributes a scheduling result of the resource assignment calculation unit as resource assignment information or sleepable time information to each functional unit that is a part of the base station and is capable of sleeping.

Abstract: A server delay controller includes: a sleep management unit that makes a thread sleep when no packet arrives for a predetermined period and cancels the sleep of the thread with a hardware interrupt when the packet arrives; a HW interrupt frequency management table that stores the number of times of hardware interrupt; and a HW interrupt frequency control unit that calculates a HW interrupt frequency on the basis of the number of times of hardware interrupt and controls HW interrupt permission or prohibition by sleep of the sleep management unit on the basis of the calculated HW interrupt frequency.

Abstract: A server delay control device includes: a data arrival notifier that notifies a data processing APL of data acquired by a data arrival monitor and passes the data to the data processing APL (1); and a manager that causes a polling thread to sleep and cancels sleep of the polling thread by a hardware interrupt when a packet arrives, and the manager controls a timing of the sleep by permitting the hardware interrupt on the basis of characteristics of an application program.