Patents by Inventor Ko Nishimura

Ko Nishimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9727121
    Abstract: A wireless communication device includes a processor, a memory unit capable of retaining data in a power saving state, a clock control unit configured to control when a clock is to be supplied to each pair of processor and memory, and a power control unit configured to control an amount of power to be supplied to the processor and the memory unit. In the power saving state, the clock control unit stops supplying the clock to the processor and the memory unit, and the power control unit reduces the amount of power supplied to the memory unit. When returning from the power saving state, the power control unit increases the amount of power supplied to the memory unit, and the clock control unit starts supplying the clock to the memory unit before starting to supply the clock to the processor.
    Type: Grant
    Filed: August 26, 2015
    Date of Patent: August 8, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Ko Nishimura
  • Publication number: 20160259396
    Abstract: A wireless communication device includes a processor, a memory unit capable of retaining data in a power saving state, a clock control unit configured to control when a clock is to be supplied to each pair of processor and memory, and a power control unit configured to control an amount of power to be supplied to the processor and the memory unit. In the power saving state, the clock control unit stops supplying the clock to the processor and the memory unit, and the power control unit reduces the amount of power supplied to the memory unit. When returning from the power saving state, the power control unit increases the amount of power supplied to the memory unit, and the clock control unit starts supplying the clock to the memory unit before starting to supply the clock to the processor.
    Type: Application
    Filed: August 26, 2015
    Publication date: September 8, 2016
    Inventor: Ko NISHIMURA
  • Patent number: 8614397
    Abstract: In a circuit device of the present invention, the lower surface side of a circuit board is covered with a second resin encapsulant, and the upper surface side and the like of the circuit board are covered with a first resin encapsulant. Since heat dissipation to the outside of the circuit device is achieved mainly through the second resin encapsulant, a particle size of filler contained in the second resin encapsulant is made larger than a particle size of filler contained in the first resin encapsulant. Heat dissipation to the outside of the circuit device is greatly improved.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: December 24, 2013
    Assignee: ON Semiconductor Trading, Ltd.
    Inventors: Katsuyoshi Mino, Akira Iwabuchi, Ko Nishimura, Masami Motegi
  • Patent number: 8481367
    Abstract: Provided is a method of manufacturing a circuit device in which a circuit element is resin-sealed with sealing resins formed integrally with each other. In the present invention, a resin sheet and a circuit board are housed in a cavity of a mold, and thereafter a first sealing resin formed of a tablet in melted form is injected into the cavity. At the time of injecting the first sealing resin, a second sealing resin formed of the resin sheet in melted form is not yet cured and is maintained in liquid form. Accordingly, the injected first sealing resin and the second sealing resin are mixed at the boundary therebetween, preventing the generation of a gap in the boundary portion and therefore preventing the deterioration of the moisture resistance and withstand voltage at the boundary portion.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: July 9, 2013
    Assignee: ON Semiconductor Trading, Ltd.
    Inventors: Katsuyoshi Mino, Akira Iwabuchi, Ko Nishimura
  • Publication number: 20120018202
    Abstract: In a circuit device of the present invention, the lower surface side of a circuit board is covered with a second resin encapsulant, and the upper surface side and the like of the circuit board are covered with a first resin encapsulant. Since heat dissipation to the outside of the circuit device is achieved mainly through the second resin encapsulant, a particle size of filler contained in the second resin encapsulant is made larger than a particle size of filler contained in the first resin encapsulant. Heat dissipation to the outside of the circuit device is greatly improved.
    Type: Application
    Filed: July 22, 2011
    Publication date: January 26, 2012
    Applicant: ON Semiconductor Trading, Ltd.
    Inventors: Katsuyoshi MINO, Akira Iwabuchi, Ko Nishimura, Masami Motegi
  • Publication number: 20120021568
    Abstract: Provided is a method of manufacturing a circuit device in which a circuit element is resin-sealed with sealing resins formed integrally with each other. In the present invention, a resin sheet and a circuit board are housed in a cavity of a mold, and thereafter a first sealing resin formed of a tablet in melted form is injected into the cavity. At the time of injecting the first sealing resin, a second sealing resin formed of the resin sheet in melted form is not yet cured and is maintained in liquid form. Accordingly, the injected first sealing resin and the second sealing resin are mixed at the boundary therebetween, preventing the generation of a gap in the boundary portion and therefore preventing the deterioration of the moisture resistance and withstand voltage at the boundary portion.
    Type: Application
    Filed: July 22, 2011
    Publication date: January 26, 2012
    Applicant: ON Semiconductor Trading, Ltd.
    Inventors: Katsuyoshi Mino, Akira Iwabuchi, Ko Nishimura