Abstract: A device and method for fabrication includes providing a first substrate assembly including a first substrate and a first metal layer formed on the first substrate and a second substrate assembly including a second substrate and a second metal layer formed on the second substrate. The first metal layer is joined to the second metal layer using a cold welding process wherein one of the first substrate and the second substrate includes a semiconductor channel layer for forming a transistor device.

Abstract: Field Effect Transistors (FETs), Integrated Circuit (IC) chips including the FETs, and a method of forming the FETs and IC. FET locations define FET pedestals on a layered semiconductor wafer that may include a III-V semiconductor surface layer, e.g., Gallium Arsenide (GaAs), and a buried layer, e.g., Aluminum Arsenide (AlAs). A dielectric material, e.g., Aluminum Oxide (AlO), surrounds pedestals at least in FET source/drain regions. A conductive cap caps channel sidewalls at opposite channel ends. III-V on insulator (IIIVOI) devices form wherever the dielectric material layer is thicker than half the device length. Source/drain contacts are formed to the caps and terminate in/above the dielectric material in the buried layer.

Abstract: A light emitting diode of the invention via laser scribing method is used to build up the mesh texture on the backside of the sapphire of light emitting diodes. Then high reflectivity and thermal conductivity metals are deposited onto the mesh structure. Since the multiple-reflection from the texture, the light extraction efficiency will be increased. Meanwhile, the high thermal conductivity metal filled into the sapphire also lead to the better heat dissipation within the light emitting diodes, it will decrease the junction temperature and avoid the thermal effect to reduce light efficiency and the lifetime.