Patents by Inventor Ko-Wei Lin
Ko-Wei Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240131538Abstract: An annular airflow regulating apparatus includes a cup-shaped element and an adjustment element. The cup-shaped element has a bowl and a bottom, integrated to form a first chamber. The bottom has a tapered channel parallel to an axis and penetrating through the bottom. A ring-shaped groove is disposed between the tapered channel and the bottom. The ring-shaped groove has an annular plane perpendicular to the axis. The adjustment element, having a tapered portion and second holes, is movably disposed in the cup-shaped element. The tapered portion protrudes into the tapered channel A tapered annular gap is formed between the tapered portion and the tapered channel. When the adjustment element is moved with respect to the cup-shaped element, a width of the tapered annular gap is varied, and thereupon a flow rate and velocity of the process gas would be varied accordingly.Type: ApplicationFiled: December 8, 2022Publication date: April 25, 2024Inventors: CHEN-CHUNG DU, Ming-Jyh Chang, Chang-Yi Chen, Ming-Hau Tsai, Ko-Chieh chao, Yi-Wei Lin
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Patent number: 11929722Abstract: The present invention provides an audio control circuit comprising an USB interface and a processing circuit is disclosed. The USB interface is used to connect to a host device, and the processing circuit is configured to perform enumeration with the host device via the USB interface, and the processing circuit is further configured to determine if the host device operates in a BIOS stage or an operating system stage to generate a control signal according to packets of the enumeration. When the processing circuit determines that the host device operates in the BIOS stage, the processing circuit generates the control signal to enable a de-pop circuit; and when the processing circuit determines that the host device operates in the operating system stage, the processing circuit generates the control signal to disable the de-pop circuit.Type: GrantFiled: June 30, 2021Date of Patent: March 12, 2024Assignee: Realtek Semiconductor Corp.Inventors: Ko-Wei Chen, Lun-Cheng Tsao, Chi-Yih Lin
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Patent number: 11856870Abstract: A magnetoresistive random access memory (MRAM) structure includes a magnetic tunnel junction (MTJ), and a top electrode which contacts an end of the MTJ. The top electrode includes a top electrode upper portion and a top electrode lower portion. The width of the top electrode upper portion is larger than the width of the top electrode lower portion. A bottom electrode contacts another end of the MTJ. The top electrode, the MTJ and the bottom electrode form an MRAM.Type: GrantFiled: June 21, 2022Date of Patent: December 26, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Kuo-Chih Lai, Yi-Syun Chou, Ko-Wei Lin, Pei-Hsun Kao, Wei Chen, Chia-Fu Cheng, Chun-Yao Yang, Chia-Chang Hsu
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Publication number: 20230238445Abstract: A high electron mobility transistor (HEMT) includes a substrate, a channel layer, a barrier layer and a passivation layer. A contact structure is disposed on the passivation layer and extends through the passivation layer and the barrier layer to directly contact the channel layer. The contact structure includes a metal layer, and the metal layer includes a metal material doped with a first additive. A weight percentage of the first additive in the metal layer is between 0% and 2%.Type: ApplicationFiled: February 20, 2022Publication date: July 27, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Ko-Wei Lin, Chun-Chieh Chiu, Chun-Ling Lin, Shu Min Huang, Hsin-Fu Huang
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Publication number: 20220320420Abstract: A magnetoresistive random access memory (MRAM) structure includes a magnetic tunnel junction (MTJ), and a top electrode which contacts an end of the MTJ. The top electrode includes a top electrode upper portion and a top electrode lower portion. The width of the top electrode upper portion is larger than the width of the top electrode lower portion. A bottom electrode contacts another end of the MTJ. The top electrode, the MTJ and the bottom electrode form an MRAM.Type: ApplicationFiled: June 21, 2022Publication date: October 6, 2022Applicant: UNITED MICROELECTRONICS CORP.Inventors: Kuo-Chih Lai, Yi-Syun Chou, Ko-Wei Lin, Pei-Hsun Kao, Wei Chen, Chia-Fu Cheng, Chun-Yao Yang, Chia-Chang Hsu
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Patent number: 11404631Abstract: A magnetoresistive random access memory (MRAM) structure includes a magnetic tunnel junction (MTJ), and a top electrode which contacts an end of the MTJ. The top electrode includes a top electrode upper portion and a top electrode lower portion. The width of the top electrode upper portion is larger than the width of the top electrode lower portion. A bottom electrode contacts another end of the MTJ. The top electrode, the MTJ and the bottom electrode form an MRAM.Type: GrantFiled: July 9, 2019Date of Patent: August 2, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Kuo-Chih Lai, Yi-Syun Chou, Ko-Wei Lin, Pei-Hsun Kao, Wei Chen, Chia-Fu Cheng, Chun-Yao Yang, Chia-Chang Hsu
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Publication number: 20200403144Abstract: A magnetoresistive random access memory (MRAM) structure includes a magnetic tunnel junction (MTJ), and a top electrode which contacts an end of the MTJ. The top electrode includes a top electrode upper portion and a top electrode lower portion. The width of the top electrode upper portion is larger than the width of the top electrode lower portion. A bottom electrode contacts another end of the MTJ. The top electrode, the MTJ and the bottom electrode form an MRAM.Type: ApplicationFiled: July 9, 2019Publication date: December 24, 2020Inventors: Kuo-Chih Lai, Yi-Syun Chou, Ko-Wei Lin, Pei-Hsun Kao, Wei Chen, Chia-Fu Cheng, Chun-Yao Yang, Chia-Chang Hsu
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Patent number: 10756128Abstract: An integrated circuit device includes a complementary metal oxide semiconductor (CMOS) image sensor. The complementary metal oxide semiconductor (CMOS) image sensor includes a P-N junction photodiode, a transistor gate, a polysilicon plug and a stacked metal layer. The P-N junction photodiode is disposed in a substrate. The transistor gate and the polysilicon plug are disposed on the substrate, wherein the polysilicon plug is directly connected to the P-N junction photodiode. The stacked metal layer connects the polysilicon plug to the transistor gate, wherein the stacked metal layer includes a lower metal layer and an upper metal layer, and the lower metal layer includes a first metal silicide part contacting to the polysilicon plug. The present invention also provides a method of fabricating said integrated circuit device.Type: GrantFiled: January 10, 2019Date of Patent: August 25, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Kuo-Chih Lai, Shih-Min Chou, Ko-Wei Lin, Chin-Fu Lin, Wei-Chuan Tsai, Chun-Yao Yang, Chia-Fu Cheng, Yi-Syun Chou, Wei Chen
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Publication number: 20200212090Abstract: An integrated circuit device includes a complementary metal oxide semiconductor (CMOS) image sensor. The complementary metal oxide semiconductor (CMOS) image sensor includes a P-N junction photodiode, a transistor gate, a polysilicon plug and a stacked metal layer. The P-N junction photodiode is disposed in a substrate. The transistor gate and the polysilicon plug are disposed on the substrate, wherein the polysilicon plug is directly connected to the P-N junction photodiode. The stacked metal layer connects the polysilicon plug to the transistor gate, wherein the stacked metal layer includes a lower metal layer and an upper metal layer, and the lower metal layer includes a first metal silicide part contacting to the polysilicon plug. The present invention also provides a method of fabricating said integrated circuit device.Type: ApplicationFiled: January 10, 2019Publication date: July 2, 2020Inventors: Kuo-Chih Lai, Shih-Min Chou, Ko-Wei Lin, Chin-Fu Lin, Wei-Chuan Tsai, Chun-Yao Yang, Chia-Fu Cheng, Yi-Syun Chou, Wei Chen
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Publication number: 20200168450Abstract: A method for fabricating interconnect of semiconductor device. The method includes providing a base substrate, having an inter-layer dielectric layer on top. A copper interconnect structure is formed in the inter-layer dielectric layer. A pre-sputter clean process is performed with hydrogen radicals on the copper interconnect structure. A degas process is sequentially performed on the copper interconnect structure. A cobalt cap layer is formed on the copper interconnect structure.Type: ApplicationFiled: November 28, 2018Publication date: May 28, 2020Applicant: United Microelectronics Corp.Inventors: Ko-Wei Lin, Kuan-Hsiang Chen, Hsin-Fu Huang, Chun-Ling Lin, Sheng-Yi Su, Pei-Hsun Kao
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Patent number: 10446489Abstract: An interconnect structure includes a dielectric layer and a conductor embedded in the dielectric layer. A top surface of the conductor is flush with a top surface of the dielectric layer. A cobalt cap layer is deposited on the top surface of the conductor. A nitrogen-doped cobalt layer is disposed on the cobalt cap layer.Type: GrantFiled: October 25, 2018Date of Patent: October 15, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ko-Wei Lin, Hung-Miao Lin, Chun-Ling Lin, Ying-Lien Chen, Huei-Ru Tsai, Sheng-Yi Su
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Publication number: 20190067184Abstract: An interconnect structure includes a dielectric layer and a conductor embedded in the dielectric layer. A top surface of the conductor is flush with a top surface of the dielectric layer. A cobalt cap layer is deposited on the top surface of the conductor. A nitrogen-doped cobalt layer is disposed on the cobalt cap layer.Type: ApplicationFiled: October 25, 2018Publication date: February 28, 2019Inventors: Ko-Wei Lin, Hung-Miao Lin, Chun-Ling Lin, Ying-Lien Chen, Huei-Ru Tsai, Sheng-Yi Su
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Patent number: 10153231Abstract: An interconnect structure includes a dielectric layer and a conductor embedded in the dielectric layer. A top surface of the conductor is flush with a top surface of the dielectric layer. A cobalt cap layer is deposited on the top surface of the conductor. A nitrogen-doped cobalt layer is disposed on the cobalt cap layer.Type: GrantFiled: March 22, 2017Date of Patent: December 11, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ko-Wei Lin, Hung-Miao Lin, Chun-Ling Lin, Ying-Lien Chen, Huei-Ru Tsai, Sheng-Yi Su
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Patent number: 10079177Abstract: A method is provided for forming copper material over a substrate. The method includes forming a barrier layer over a substrate. Then, a depositing-soaking-treatment (DST) process is performed over the barrier layer. A copper layer is formed on the cobalt layer. The DST process includes depositing a cobalt layer on the barrier layer. Then, the cobalt layer is soaked with H2 gas at a first pressure. The cobalt layer is treated with a H2 plasma at a second pressure. The second pressure is lower than the first pressure.Type: GrantFiled: September 1, 2017Date of Patent: September 18, 2018Assignee: United Microelectronics Corp.Inventors: Ko-Wei Lin, Ying-Lien Chen, Chun-Ling Lin, Huei-Ru Tsai, Hung-Miao Lin, Sheng-Yi Su, Tzu-Hao Liu
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Publication number: 20180261537Abstract: An interconnect structure includes a dielectric layer and a conductor embedded in the dielectric layer. A top surface of the conductor is flush with a top surface of the dielectric layer. A cobalt cap layer is deposited on the top surface of the conductor. A nitrogen-doped cobalt layer is disposed on the cobalt cap layer.Type: ApplicationFiled: March 22, 2017Publication date: September 13, 2018Inventors: Ko-Wei Lin, Hung-Miao Lin, Chun-Ling Lin, Ying-Lien Chen, Huei-Ru Tsai, Sheng-Yi Su
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Publication number: 20180138263Abstract: A semiconductor structure includes a capacitor. The capacitor includes a bottom electrode, a first high-k dielectric layer, a second high-k dielectric layer and a top electrode. The bottom electrode includes a first layer and a second layer disposed on the first layer. The bottom electrode is formed of TiN. The first layer has a crystallization structure. The second layer has an amorphous structure. The first high-k dielectric layer is disposed on the bottom electrode. The first high-k dielectric layer is formed of TiO2. The second high-k dielectric layer is disposed on the first high-k dielectric layer. The second high-k dielectric layer is formed of a material different from TiO2. The top electrode is disposed on the second high-k dielectric layer.Type: ApplicationFiled: November 14, 2016Publication date: May 17, 2018Inventors: Ko-Wei Lin, Yen-Chen Chen, Chin-Fu Lin, Chun-Yuan Wu, Chun-Ling Lin
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Patent number: 9966425Abstract: A method for fabricating a metal-insulator-metal (MIM) capacitor includes the steps of: forming a capacitor bottom metal (CBM) layer on a material layer; forming a silicon layer on the CBM layer; forming a capacitor dielectric layer on the silicon layer; and forming a capacitor top metal (CTM) layer on the capacitor dielectric layer.Type: GrantFiled: February 28, 2017Date of Patent: May 8, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Jen-Po Huang, Chin-Fu Lin, Bin-Siang Tsai, Xu Yang Shen, Seng Wah Liau, Yen-Chen Chen, Ko-Wei Lin, Chun-Ling Lin, Kuo-Chih Lai, Ai-Sen Liu, Chun-Yuan Wu, Yang-Ju Lu
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Publication number: 20140012943Abstract: A method and a storage apparatus for switching a data transmission path to transmit data are provided. The storage apparatus comprises a storage element, an interface connector, a connector control interface connected with the storage element and the interface connector, a wireless transmission module, and an apparatus controller connected with the storage element and the wireless transmission module. In the method, the apparatus controller receives a connection request from a remote apparatus by using the wireless transmission module, and accordingly transmits an inquiry message to the remote apparatus to ask whether to establish a wireless data transmission path. When a confirmation message returned from the remote apparatus is received, the apparatus controller closes the connector control interface and establishes a wireless data transmission path to provide the remote apparatus to access the data in the storage element.Type: ApplicationFiled: May 10, 2013Publication date: January 9, 2014Applicant: COMPAL ELECTRONICS, INC.Inventors: Chung-Jen Yang, Yung-Chih Tsao, Shin-Che Feng, Ko-Wei Lin, Wen-Sheng Chang, Chang-Ching Hung, Chia-Chun Chang
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Patent number: 8389869Abstract: A circuit board including a substrate, a conductive pattern and a solder mask layer is provided. The conductive pattern includes a pad, a tail trace and a signal trace. The tail trace connects with the edge of the pad and the signal trace connects with the edge of the pad. An angle between a portion of the signal trace neighboring the pad and the tail trace is larger than 0 degree and smaller than 180 degree. The solder mask layer is disposed on the substrate and covers a portion of conductive pattern. The solder mask layer has an opening exposing the whole pad.Type: GrantFiled: September 4, 2009Date of Patent: March 5, 2013Assignee: Advanced Semiconductor Engineering, Inc.Inventor: Ko-Wei Lin
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Patent number: 8089164Abstract: The present invention relates to a substrate having optional circuits and a structure of flip chip bonding. The substrate includes a substrate body, at least one substrate pad, a first conductive trace and a second conductive trace. The substrate body has a surface. The substrate pad is disposed on the surface of the substrate body. The first conductive trace is connected to a first circuit, and has a first breaking area so it forms a discontinuous line. The second conductive trace is connected to a second circuit, and has a second breaking area so tit forms a discontinuous line. The second conductive trace and the first conductive trace are connected to the same substrate pad. Thus, the substrate can choose to connect different circuits, so the substrate can be applied to different products by connecting the desired circuit, thus reducing the manufacturing cost.Type: GrantFiled: September 23, 2009Date of Patent: January 3, 2012Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Ko-Wei Lin, Yun-Hsiang Tien, Kun-Ting Hung