Patents by Inventor Ko-Wei Lin

Ko-Wei Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200403144
    Abstract: A magnetoresistive random access memory (MRAM) structure includes a magnetic tunnel junction (MTJ), and a top electrode which contacts an end of the MTJ. The top electrode includes a top electrode upper portion and a top electrode lower portion. The width of the top electrode upper portion is larger than the width of the top electrode lower portion. A bottom electrode contacts another end of the MTJ. The top electrode, the MTJ and the bottom electrode form an MRAM.
    Type: Application
    Filed: July 9, 2019
    Publication date: December 24, 2020
    Inventors: Kuo-Chih Lai, Yi-Syun Chou, Ko-Wei Lin, Pei-Hsun Kao, Wei Chen, Chia-Fu Cheng, Chun-Yao Yang, Chia-Chang Hsu
  • Patent number: 10756128
    Abstract: An integrated circuit device includes a complementary metal oxide semiconductor (CMOS) image sensor. The complementary metal oxide semiconductor (CMOS) image sensor includes a P-N junction photodiode, a transistor gate, a polysilicon plug and a stacked metal layer. The P-N junction photodiode is disposed in a substrate. The transistor gate and the polysilicon plug are disposed on the substrate, wherein the polysilicon plug is directly connected to the P-N junction photodiode. The stacked metal layer connects the polysilicon plug to the transistor gate, wherein the stacked metal layer includes a lower metal layer and an upper metal layer, and the lower metal layer includes a first metal silicide part contacting to the polysilicon plug. The present invention also provides a method of fabricating said integrated circuit device.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: August 25, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kuo-Chih Lai, Shih-Min Chou, Ko-Wei Lin, Chin-Fu Lin, Wei-Chuan Tsai, Chun-Yao Yang, Chia-Fu Cheng, Yi-Syun Chou, Wei Chen
  • Publication number: 20200212090
    Abstract: An integrated circuit device includes a complementary metal oxide semiconductor (CMOS) image sensor. The complementary metal oxide semiconductor (CMOS) image sensor includes a P-N junction photodiode, a transistor gate, a polysilicon plug and a stacked metal layer. The P-N junction photodiode is disposed in a substrate. The transistor gate and the polysilicon plug are disposed on the substrate, wherein the polysilicon plug is directly connected to the P-N junction photodiode. The stacked metal layer connects the polysilicon plug to the transistor gate, wherein the stacked metal layer includes a lower metal layer and an upper metal layer, and the lower metal layer includes a first metal silicide part contacting to the polysilicon plug. The present invention also provides a method of fabricating said integrated circuit device.
    Type: Application
    Filed: January 10, 2019
    Publication date: July 2, 2020
    Inventors: Kuo-Chih Lai, Shih-Min Chou, Ko-Wei Lin, Chin-Fu Lin, Wei-Chuan Tsai, Chun-Yao Yang, Chia-Fu Cheng, Yi-Syun Chou, Wei Chen
  • Publication number: 20200168450
    Abstract: A method for fabricating interconnect of semiconductor device. The method includes providing a base substrate, having an inter-layer dielectric layer on top. A copper interconnect structure is formed in the inter-layer dielectric layer. A pre-sputter clean process is performed with hydrogen radicals on the copper interconnect structure. A degas process is sequentially performed on the copper interconnect structure. A cobalt cap layer is formed on the copper interconnect structure.
    Type: Application
    Filed: November 28, 2018
    Publication date: May 28, 2020
    Applicant: United Microelectronics Corp.
    Inventors: Ko-Wei Lin, Kuan-Hsiang Chen, Hsin-Fu Huang, Chun-Ling Lin, Sheng-Yi Su, Pei-Hsun Kao
  • Patent number: 10446489
    Abstract: An interconnect structure includes a dielectric layer and a conductor embedded in the dielectric layer. A top surface of the conductor is flush with a top surface of the dielectric layer. A cobalt cap layer is deposited on the top surface of the conductor. A nitrogen-doped cobalt layer is disposed on the cobalt cap layer.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: October 15, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ko-Wei Lin, Hung-Miao Lin, Chun-Ling Lin, Ying-Lien Chen, Huei-Ru Tsai, Sheng-Yi Su
  • Publication number: 20190067184
    Abstract: An interconnect structure includes a dielectric layer and a conductor embedded in the dielectric layer. A top surface of the conductor is flush with a top surface of the dielectric layer. A cobalt cap layer is deposited on the top surface of the conductor. A nitrogen-doped cobalt layer is disposed on the cobalt cap layer.
    Type: Application
    Filed: October 25, 2018
    Publication date: February 28, 2019
    Inventors: Ko-Wei Lin, Hung-Miao Lin, Chun-Ling Lin, Ying-Lien Chen, Huei-Ru Tsai, Sheng-Yi Su
  • Patent number: 10153231
    Abstract: An interconnect structure includes a dielectric layer and a conductor embedded in the dielectric layer. A top surface of the conductor is flush with a top surface of the dielectric layer. A cobalt cap layer is deposited on the top surface of the conductor. A nitrogen-doped cobalt layer is disposed on the cobalt cap layer.
    Type: Grant
    Filed: March 22, 2017
    Date of Patent: December 11, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ko-Wei Lin, Hung-Miao Lin, Chun-Ling Lin, Ying-Lien Chen, Huei-Ru Tsai, Sheng-Yi Su
  • Patent number: 10079177
    Abstract: A method is provided for forming copper material over a substrate. The method includes forming a barrier layer over a substrate. Then, a depositing-soaking-treatment (DST) process is performed over the barrier layer. A copper layer is formed on the cobalt layer. The DST process includes depositing a cobalt layer on the barrier layer. Then, the cobalt layer is soaked with H2 gas at a first pressure. The cobalt layer is treated with a H2 plasma at a second pressure. The second pressure is lower than the first pressure.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: September 18, 2018
    Assignee: United Microelectronics Corp.
    Inventors: Ko-Wei Lin, Ying-Lien Chen, Chun-Ling Lin, Huei-Ru Tsai, Hung-Miao Lin, Sheng-Yi Su, Tzu-Hao Liu
  • Publication number: 20180261537
    Abstract: An interconnect structure includes a dielectric layer and a conductor embedded in the dielectric layer. A top surface of the conductor is flush with a top surface of the dielectric layer. A cobalt cap layer is deposited on the top surface of the conductor. A nitrogen-doped cobalt layer is disposed on the cobalt cap layer.
    Type: Application
    Filed: March 22, 2017
    Publication date: September 13, 2018
    Inventors: Ko-Wei Lin, Hung-Miao Lin, Chun-Ling Lin, Ying-Lien Chen, Huei-Ru Tsai, Sheng-Yi Su
  • Publication number: 20180138263
    Abstract: A semiconductor structure includes a capacitor. The capacitor includes a bottom electrode, a first high-k dielectric layer, a second high-k dielectric layer and a top electrode. The bottom electrode includes a first layer and a second layer disposed on the first layer. The bottom electrode is formed of TiN. The first layer has a crystallization structure. The second layer has an amorphous structure. The first high-k dielectric layer is disposed on the bottom electrode. The first high-k dielectric layer is formed of TiO2. The second high-k dielectric layer is disposed on the first high-k dielectric layer. The second high-k dielectric layer is formed of a material different from TiO2. The top electrode is disposed on the second high-k dielectric layer.
    Type: Application
    Filed: November 14, 2016
    Publication date: May 17, 2018
    Inventors: Ko-Wei Lin, Yen-Chen Chen, Chin-Fu Lin, Chun-Yuan Wu, Chun-Ling Lin
  • Patent number: 9966425
    Abstract: A method for fabricating a metal-insulator-metal (MIM) capacitor includes the steps of: forming a capacitor bottom metal (CBM) layer on a material layer; forming a silicon layer on the CBM layer; forming a capacitor dielectric layer on the silicon layer; and forming a capacitor top metal (CTM) layer on the capacitor dielectric layer.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: May 8, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Jen-Po Huang, Chin-Fu Lin, Bin-Siang Tsai, Xu Yang Shen, Seng Wah Liau, Yen-Chen Chen, Ko-Wei Lin, Chun-Ling Lin, Kuo-Chih Lai, Ai-Sen Liu, Chun-Yuan Wu, Yang-Ju Lu
  • Publication number: 20140012943
    Abstract: A method and a storage apparatus for switching a data transmission path to transmit data are provided. The storage apparatus comprises a storage element, an interface connector, a connector control interface connected with the storage element and the interface connector, a wireless transmission module, and an apparatus controller connected with the storage element and the wireless transmission module. In the method, the apparatus controller receives a connection request from a remote apparatus by using the wireless transmission module, and accordingly transmits an inquiry message to the remote apparatus to ask whether to establish a wireless data transmission path. When a confirmation message returned from the remote apparatus is received, the apparatus controller closes the connector control interface and establishes a wireless data transmission path to provide the remote apparatus to access the data in the storage element.
    Type: Application
    Filed: May 10, 2013
    Publication date: January 9, 2014
    Applicant: COMPAL ELECTRONICS, INC.
    Inventors: Chung-Jen Yang, Yung-Chih Tsao, Shin-Che Feng, Ko-Wei Lin, Wen-Sheng Chang, Chang-Ching Hung, Chia-Chun Chang
  • Patent number: 8389869
    Abstract: A circuit board including a substrate, a conductive pattern and a solder mask layer is provided. The conductive pattern includes a pad, a tail trace and a signal trace. The tail trace connects with the edge of the pad and the signal trace connects with the edge of the pad. An angle between a portion of the signal trace neighboring the pad and the tail trace is larger than 0 degree and smaller than 180 degree. The solder mask layer is disposed on the substrate and covers a portion of conductive pattern. The solder mask layer has an opening exposing the whole pad.
    Type: Grant
    Filed: September 4, 2009
    Date of Patent: March 5, 2013
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventor: Ko-Wei Lin
  • Patent number: 8089164
    Abstract: The present invention relates to a substrate having optional circuits and a structure of flip chip bonding. The substrate includes a substrate body, at least one substrate pad, a first conductive trace and a second conductive trace. The substrate body has a surface. The substrate pad is disposed on the surface of the substrate body. The first conductive trace is connected to a first circuit, and has a first breaking area so it forms a discontinuous line. The second conductive trace is connected to a second circuit, and has a second breaking area so tit forms a discontinuous line. The second conductive trace and the first conductive trace are connected to the same substrate pad. Thus, the substrate can choose to connect different circuits, so the substrate can be applied to different products by connecting the desired circuit, thus reducing the manufacturing cost.
    Type: Grant
    Filed: September 23, 2009
    Date of Patent: January 3, 2012
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Ko-Wei Lin, Yun-Hsiang Tien, Kun-Ting Hung
  • Publication number: 20100212948
    Abstract: A circuit board including a substrate, a conductive pattern and a solder mask layer is provided. The conductive pattern includes a pad, a tail trace and a signal trace. The tail trace connects with the edge of the pad and the signal trace connects with the edge of the pad. An angle between a portion of the signal trace neighboring the pad and the tail trace is larger than 0 degree and smaller than 180 degree. The solder mask layer is disposed on the substrate and covers a portion of conductive pattern. The solder mask layer has an opening exposing the whole pad.
    Type: Application
    Filed: September 4, 2009
    Publication date: August 26, 2010
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Ko-Wei Lin
  • Publication number: 20100176516
    Abstract: The present invention relates to a substrate having optional circuits and a structure of flip chip bonding. The substrate includes a substrate body, at least one substrate pad, a first conductive trace and a second conductive trace. The substrate body has a surface. The substrate pad is disposed on the surface of the substrate body. The first conductive trace is connected to a first circuit, and has a first breaking area so it forms a discontinuous line. The second conductive trace is connected to a second circuit, and has a second breaking area so tit forms a discontinuous line. The second conductive trace and the first conductive trace are connected to the same substrate pad. Thus, the substrate can choose to connect different circuits, so the substrate can be applied to different products by connecting the desired circuit, thus reducing the manufacturing cost.
    Type: Application
    Filed: September 23, 2009
    Publication date: July 15, 2010
    Inventors: Ko-Wei Lin, Yun-Hsiang Tien, Kun-Ting Hung