Patents by Inventor Ko-Yi Lee
Ko-Yi Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190139916Abstract: A package structure includes at least one semiconductor chip, an insulating encapsulation, and a redistribution circuit structure. The semiconductor chip has an active surface and connecting pads distributed thereon. The insulating encapsulation encapsulates the semiconductor chip. The redistribution circuit structure is disposed on and has at least one metallization layer with metal segments, wherein the redistribution circuit structure is electrically connected to the semiconductor chip through the at least one metallization layer and the connecting pads electrically connected thereto. A projection location of a first gap between any two most adjacent connecting pads of the connecting pads is partially overlapped with a projection location of a second gap between any two most adjacent metal segments of the metal segments of the at least one metallization layer in a vertical projection on the active surface of the at least one semiconductor chip.Type: ApplicationFiled: July 6, 2018Publication date: May 9, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsi-Yu Kuo, Ko-Yi Lee, Yu-Lin Chu
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Patent number: 10283468Abstract: A package structure includes at least one semiconductor chip, an insulating encapsulation, and a redistribution circuit structure. The semiconductor chip has an active surface and connecting pads distributed thereon. The insulating encapsulation encapsulates the semiconductor chip. The redistribution circuit structure is disposed on and has at least one metallization layer with metal segments, wherein the redistribution circuit structure is electrically connected to the semiconductor chip through the at least one metallization layer and the connecting pads electrically connected thereto. A projection location of a first gap between any two most adjacent connecting pads of the connecting pads is partially overlapped with a projection location of a second gap between any two most adjacent metal segments of the metal segments of the at least one metallization layer in a vertical projection on the active surface of the at least one semiconductor chip.Type: GrantFiled: July 6, 2018Date of Patent: May 7, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsi-Yu Kuo, Ko-Yi Lee, Yu-Lin Chu
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Publication number: 20180275812Abstract: A touch screen data transmission system enabling a single touch screen to communicate with and command a plurality of hosts includes a dividing module, an obtaining module, a determining module, a converting module, and a transmitting module. The dividing module divides the touch screen into a plurality of touch areas which each have own start and end coordinates and each touch area is relevant to one host of the plurality. The obtaining module obtains a coordinate of a touch point and determining module determines the relevant touch area. The converting module converts the coordinate into an area coordinate and the transmitting module transmits the area coordinate to relevant host to open that host for communicating and commanding purposes. A touch screen data transmission method and a split touch device are also provided.Type: ApplicationFiled: March 31, 2017Publication date: September 27, 2018Inventors: KO-YI LEE, HSIN-TE YU, QIU-HUANG CHEN, YUAN-CHIEH TSAI
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Patent number: 10085204Abstract: A data transmission system includes a device and a base. The base includes a near field communication (NFC) module and a processing module configured to determine whether a wireless network exits. The NFC module includes a determining unit configured to determine whether the NFC module writes a predetermined tag after the processing module determines the wireless network exits and configured to determine whether the predetermined tag is an authorization code, a sending unit configured to send a service set identifier (SSID) and a password to the device after the predetermined tag is the authorization code, and a control unit configured to switch an input mode of the base to a wireless network mode after the SSID and the password are sent to the device. The device is configured to be connected to the wireless network after receiving the SSID and the password. A communication method is also provided.Type: GrantFiled: May 19, 2015Date of Patent: September 25, 2018Assignees: HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD., HON HAI PRECISION INDUSTRY CO., LTD.Inventors: Chi-Kang Chiang, Wei-Ting Lin, Ru-Me Na Jiang, Al-Guo Cheng, Ko-Yi Lee, Ping-Chuan Tsai, Jing-Hu Song, Shuo-Hsiu Chang
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Publication number: 20160278005Abstract: A data transmission system includes a device and a base. The base includes a near field communication (NFC) module and a processing module configured to determine whether a wireless network exits. The NFC module includes a determining unit configured to determine whether the NFC module writes a predetermined tag after the processing module determines the wireless network exits and configured to determine whether the predetermined tag is an authorization code, a sending unit configured to send a service set identifier (SSID) and a password to the device after the predetermined tag is the authorization code, and a control unit configured to switch an input mode of the base to a wireless network mode after the SSID and the password are sent to the device. The device is configured to be connected to the wireless network after receiving the SSID and the password. A communication method is also provided.Type: ApplicationFiled: May 19, 2015Publication date: September 22, 2016Inventors: CHI-KANG CHIANG, WEI-TING LIN, RU-ME NA JIANG, AI-GUO CHENG, KO-YI LEE, PING-CHUAN TSAI, JING-HU SONG, SHUO-HSIU CHANG
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Patent number: 9431356Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes: a substrate; a first region over the substrate, the first region comprising a first n type material; a second region over the substrate and laterally adjacent to the first region, the second region comprising a first p type material; a third region disposed within the second region and laterally separated from the first region, the third region comprising a second n type material; a fourth region disposed atop the third region, the fourth region comprising a second p type material; a fifth region disposed within the first region and laterally separated from the second region, the fifth region comprising a third p type material; and a sixth region disposed atop the fifth region, the sixth region comprising a third n type material.Type: GrantFiled: July 30, 2014Date of Patent: August 30, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsi-Yu Kuo, Ko-Yi Lee
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Publication number: 20140339676Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes: a substrate; a first region over the substrate, the first region comprising a first n type material; a second region over the substrate and laterally adjacent to the first region, the second region comprising a first p type material; a third region disposed within the second region and laterally separated from the first region, the third region comprising a second n type material; a fourth region disposed atop the third region, the fourth region comprising a second p type material; a fifth region disposed within the first region and laterally separated from the second region, the fifth region comprising a third p type material; and a sixth region disposed atop the fifth region, the sixth region comprising a third n type material.Type: ApplicationFiled: July 30, 2014Publication date: November 20, 2014Inventors: Hsi-Yu Kuo, Ko-Yi Lee
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Patent number: 7939824Abstract: A test structure to detect vertical leakage in a multi-layer flip chip pad stack or similar semiconductor device. The test structure is integrated into the semiconductor device when it is fabricated. A metal layer includes at least two portions that are electrically isolated from each other; one portion being disposed under a test pad, and another portion being disposed under a pad associated with a pad structure being tested. The metal layer in most cases is separated from a top metal layer directly underlying the pads by an inter-metal dielectric (IMD) layer. A metal layer portion underlying the pad to be tested forms a recess in which a conductive member is disposed without making electrical contact. The conductive line is electrically coupled to a test portion of the same or, alternately, of a different metal layer. The test structure may be implemented on multiple layers, with recesses portions underlying the same or different pads.Type: GrantFiled: January 15, 2009Date of Patent: May 10, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ta-Chih Peng, Yu-Ting Lin, Liang-Chen Lin, Ko-Yi Lee
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Publication number: 20090121222Abstract: A test structure to detect vertical leakage in a multi-layer flip chip pad stack or similar semiconductor device. The test structure is integrated into the semiconductor device when it is fabricated. A metal layer includes at least two portions that are electrically isolated from each other; one portion being disposed under a test pad, and another portion being disposed under a pad associated with a pad structure being tested. The metal layer in most cases is separated from a top metal layer directly underlying the pads by an inter-metal dielectric (IMD) layer. A metal layer portion underlying the pad to be tested forms a recess in which a conductive member is disposed without making electrical contact. The conductive line is electrically coupled to a test portion of the same or, alternately, of a different metal layer. The test structure may be implemented on multiple layers, with recesses portions underlying the same or different pads.Type: ApplicationFiled: January 15, 2009Publication date: May 14, 2009Inventors: Ta-Chih Peng, Yu-Ting Lin, Liang-Chen Lin, Ko-Yi Lee
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Patent number: 7498680Abstract: A test structure to detect vertical leakage in a multi-layer flip chip pad stack or similar semiconductor device. The test structure is integrated into the semiconductor device when it is fabricated. A metal layer includes at least two portions that are electrically isolated from each other; one portion being disposed under a test pad, and another portion being disposed under a pad associated with a pad structure being tested. The metal layer in most cases is separated from a top metal layer directly underlying the pads by an inter-metal dielectric (IMD) layer. A metal layer portion underlying the pad to be tested forms a recess in which a conductive member is disposed without making electrical contact. The conductive line is electrically coupled to a test portion of the same or, alternately, of a different metal layer. The test structure may be implemented on multiple layers, with recesses portions underlying the same or different pads.Type: GrantFiled: December 6, 2006Date of Patent: March 3, 2009Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ta-Chih Peng, Yu-ting Lin, Liang-Chen Lin, Ko-Yi Lee
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Publication number: 20080135840Abstract: A test structure to detect vertical leakage in a multi-layer flip chip pad stack or similar semiconductor device. The test structure is integrated into the semiconductor device when it is fabricated. A metal layer includes at least two portions that are electrically isolated from each other; one portion being disposed under a test pad, and another portion being disposed under a pad associated with a pad structure being tested. The metal layer in most cases is separated from a top metal layer directly underlying the pads by an inter-metal dielectric (IMD) layer. A metal layer portion underlying the pad to be tested forms a recess in which a conductive member is disposed without making electrical contact. The conductive line is electrically coupled to a test portion of the same or, alternately, of a different metal layer. The test structure may be implemented on multiple layers, with recesses portions underlying the same or different pads.Type: ApplicationFiled: December 6, 2006Publication date: June 12, 2008Inventors: Ta-Chih Peng, Yu-Ting Lin, Liang-Chen Lin, Ko-Yi Lee
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Publication number: 20070042593Abstract: A bonding pad structure and fabrication method thereof. A bonding pad is substantially surrounded and insulated by a dielectric layer, wherein the bonding pad is formed of at least one first conductive layer having a wiring layer with a stripe layout and a first edge portion, a second conductive layer having a wire bonding portion and a second edge portion and a plurality of plugs electrically connecting the wiring layer and the wire bonding portion. A conductive structure of an array of metal plugs or a metal damascene structure is formed to connect the first edge portion and the second edge portion, thereby preventing burn out of the first edge portion during an ESD event.Type: ApplicationFiled: October 27, 2006Publication date: February 22, 2007Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD,Inventors: Jian-Hsing Lee, Pao-Kang Niu, Ko-Yi Lee
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Patent number: 7148574Abstract: A bonding pad structure and fabrication method thereof. A bonding pad is substantially surrounded and insulated by a dielectric layer, wherein the bonding pad is formed of at least one first conductive layer having a wiring layer with a stripe layout and a first edge portion, a second conductive layer having a wire bonding portion and a second edge portion and a plurality of plugs electrically connecting the wiring layer and the wire bonding portion. A conductive structure of an array of metal plugs or a metal damascene structure is formed to connect the first edge portion and the second edge portion, thereby preventing burn out of the first edge portion during an ESD event.Type: GrantFiled: April 14, 2004Date of Patent: December 12, 2006Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jian-Hsing Lee, Pao-Kang Niu, Ko-Yi Lee
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Publication number: 20050230847Abstract: A bonding pad structure and fabrication method thereof. A bonding pad is substantially surrounded and insulated by a dielectric layer, wherein the bonding pad is formed of at least one first conductive layer having a wiring layer with a stripe layout and a first edge portion, a second conductive layer having a wire bonding portion and a second edge portion and a plurality of plugs electrically connecting the wiring layer and the wire bonding portion. A conductive structure of an array of metal plugs or a metal damascene structure is formed to connect the first edge portion and the second edge portion, thereby preventing burn out of the first edge portion during an ESD event.Type: ApplicationFiled: April 14, 2004Publication date: October 20, 2005Inventors: Jian-Hsing Lee, Pao-Kang Niu, Ko-Yi Lee