Abstract: A computation processing device includes: a convolutional computation unit that sequentially outputs convolutional computation result data; a pooling processing unit including a pooling computation circuit and a non-volatile storage circuit for pooling, in which the non-volatile storage circuit for pooling retains the convolutional computation result data or a computation result of the pooling computation circuit, as retained data, and the pooling computation circuit calculates and outputs pooling data subjected to pooling processing to a pooling region by using the retained data each time when the convolutional computation result data is input from the convolutional computation unit; and a power gating unit that blocks power supply to the non-volatile storage circuit for pooling while waiting for the input of the convolutional computation result data from the convolutional computation unit.

Abstract: A semiconductor circuit device includes a first clock gating circuit that outputs a first gated clock signal generated from a clock signal and a first enable signal, a non-volatile first flip-flop that operates in response to a clock pulse of the first gated clock signal, an acquisition circuit that acquires data inputted from the first flip-flop according to a second enable signal that enables or disables the acquisition of the data from the first flip-flop, and a power gating circuit that supplies electric power to the first flip-flop and receives the first and second enable signals as power source control signals. The power gating circuit includes a power switch, and supplies the electric power to the first flip-flop by turning ON the power switch when the power source control signals have logical values that enable the clock signal or the acquisition of the data in the acquisition circuit.

Abstract: A hazard check method and device for making hazard checks of logic circuits containing asynchronous paths and multi-cycle paths.

Abstract: A hazard check method and device for making hazard checks of logic circuits containing asynchronous paths and multi-cycle paths.

Abstract: A delay optimization designing system and method is disclosed by which reduction of outputting delay and setup time of flip-flops and clock skew can be achieved and sufficient delay optimization can be achieved. A delay optimization designing system for a logic circuit includes a flip-flop selection section for selecting any flip-flop not to be substituted into a latch from within a given logic circuit, a flip-flop searching section for searching any flip-flop having a delay margin from among the flip-flops which are not selected by the flip-flop selection section, and a latch substitution section for substituting any flip-flop searched by the flip-flop searching section into a latch which passes a signal to the output side therethrough faster than the searched flip-flop.

Abstract: A semiconductor device that helps to prevent the occurrence of current localization in the vicinity of an electrode edge and improves the reverse-recovery withstanding capability. The semiconductor device according to the invention includes a first carrier lifetime region, in which the carrier lifetime is short, formed in such a configuration that the first carrier lifetime region extends across the edge area of an anode electrode projection, which projects the anode electrode vertically into a semiconductor substrate. The first carrier lifetime region also includes a vertical boundary area spreading nearly vertically between a heavily doped p-type anode layer and a lightly doped semiconductor layer. The first carrier lifetime region of the invention is formed by irradiating with a particle beam, such as a He2+ ion beam or a proton beam.

Abstract: A delay optimization designing system and method is disclosed by which reduction of outputting delay and setup time of flip-flops and clock skew can be achieved and sufficient delay optimization can be achieved. A delay optimization designing system for a logic circuit includes a flip-flop selection section for selecting any flip-flop not to be substituted into a latch from within a given logic circuit, a flip-flop searching section for searching any flip-flop having a delay margin from among the flip-flops which are not selected by the flip-flop selection section, and a latch substitution section for substituting any flip-flop searched by the flip-flop searching section into a latch which passes a signal to the output side therethrough faster than the searched flip-flop.

Abstract: For enabling to easily and efficiently perform analysis, logical checks and revisions of a logic circuit synthesized with automatic logic circuit synthesis, an apparatus for automatically synthesizing a logic circuit according to a description of the logic circuit using a HDL comprises means (2 to 8) for generating a logic circuit (11) according to a HDL description (1) always retaining boundary information concerning of necessary intermediate signals defined in the HDL description; and a correspondence list output section (9) for outputting a correspondence list (10) describing information of each respective point of the logic circuit (11) corresponding to each of the necessary intermediate signals, by editing the boundary information. The necessary intermediate signals may be all intermediate signals defined in the HDL description (1), or may be variable intermediate signals defined in the HDL description (1) and referred to by more than a predetermined number of nodes of the logic circuit (11).