Abstract: An apparatus for applying database commands to one or more database tables includes a memory and a hardware-implemented pipeline. The hardware-implemented pipeline includes one or more table-processing circuits, and is configured to receive a stream of input records drawn from the one or more database tables, to parse first records, from among the input records, into a key and one or more fields other than the key, to store at least parts of the first records in the memory so as to be accessible using the key, and to apply a database command by matching at least parts of second records from among the input records to the at least parts of the first records stored in the memory, in accordance with the key.

Abstract: Methods and systems for efficiently processing input/output requests are provided. A network interface card (NIC) is coupled to a storage device via a peripheral link and accessible to a processor of a computing device executing instructions out of a memory device. The NIC is configured to receive a read/write request to read/write data; translate the read/write request to a storage device protocol used by the storage device coupled to the NIC; notify the storage device of the read/write request, without using the processor of the computing device, where the storage device reads/writes the data and notifies the NIC; and then the NIC prepares a response to the read/write request without having to use the processor of the computing device.

Abstract: Methods and systems for efficiently processing input/output requests are provided. A network interface card (NIC) is coupled to a storage device via a peripheral link and accessible to a processor of a computing device executing instructions out of a memory device. The NIC is configured to receive a read/write request to read/write data; translate the read/write request to a storage device protocol used by the storage device coupled to the NIC; notify the storage device of the read/write request, without using the processor of the computing device, where the storage device reads/writes the data and notifies the NIC; and then the NIC prepares a response to the read/write request without having to use the processor of the computing device.

Abstract: Certain aspects of a method and system for quality of service and congestion management for converged network interface devices are disclosed. Aspects of a method may include processing at least one of: input/output (I/O) requests and network packets in a converged network interface card (CNIC) based on a class associated with each of the I/O requests and network packets by storing on the CNIC, information that identifies the I/O requests and network packets, without storing on the I/O requests and network packets on the CNIC.

Abstract: Methods and systems for direct device access are disclosed. Aspects of one method may include a plurality of GOSs directly accessing a first network interface device, where the first network interface device may provide access to a network. One or more of the GOSs may be migrated to directly access a second network interface device, based on state information for each of the GOSs, where the state information may be maintained by the host. The GOSs may communicate data to a device coupled to the network by direct accessing the first and/or second network interface device. Similarly, the first and/or second network interface device may communicate data received from a device coupled to the network to one or more of the plurality of GOSs via direct access of the first and/or second network interface device.

Abstract: A network interface device for use with a host computer that includes a host processor and a memory, and which is configured to concurrently run a master operating system and at least one virtual operating system. The device includes a bus interface that communicates over a bus with the host processor and the memory, and a network interface, which is coupled to send and receive data packets carrying data over a packet network. A protocol processor is coupled between the bus interface and the network interface so as to convey the data between the network interface and the memory while performing protocol processing on the data packets under instructions from the at least one virtual operating system, while bypassing the master operating system.

Abstract: A network interface device includes a bus interface that communicates over a bus with a host processor and memory, and a network interface that sends and receive data packets carrying data over a packet network. A protocol processor conveys the data between the network interface and the memory via the bus interface while performing protocol offload processing on the data packets in accordance with multiple different application flows. The bus interface queues the data for transmission over the bus in a plurality of queues that are respectively assigned to the different application flows, and transmits the data over the bus according to the queues.

Abstract: A network interface device includes a bus interface that communicates over a bus with a host processor and memory, and a network interface that sends and receive data packets carrying data over a packet network. A protocol processor conveys the data between the network interface and the memory via the bus interface while performing protocol offload processing on the data packets in accordance with multiple different application flows. The bus interface queues the data for transmission over the bus in a plurality of queues that are respectively assigned to the different application flows, and transmits the data over the bus according to the queues.

Abstract: A network interface device includes a bus interface that communicates over a bus with a host processor and memory, and a network interface, including at least first and second physical ports, which are coupled to send and receive data packets carrying data over a packet network. A protocol processor includes a single transmit processing pipeline and a single receive processing pipeline, which are coupled between the bus interface and the network interface so as to convey the data between both of the first and second physical ports of the network interface and the memory via the bus interface while performing protocol offload processing on the data packets.

Abstract: A network interface device includes a bus interface that communicates over a bus with a host processor and memory, and a network interface that sends and receive data packets carrying data over a packet network. A protocol processor conveys the data between the network interface and the memory via the bus interface while performing protocol offload processing on the data packets in accordance with multiple different application flows. The bus interface queues the data for transmission over the bus in a plurality of queues that are respectively assigned to the different application flows, and transmits the data over the bus according to the queues.

Abstract: A method for communication includes inputting from a host processor to a network interface device a sequence of work requests indicative of operations to be carried out by the network interface device with respect to a plurality of the connections. The device looks ahead through the sequence in order to identify at least first and second operations that are to be carried out with respect to one of the connections in response to first and second work requests, respectively, wherein the second work request does not immediately follow the first work request in the sequence. The device loads the context data for the one of the connections from a host memory into a context cache, and performs at least the first and second operations sequentially while the context data are held in the cache.

Abstract: Certain aspects of a method and system for host memory alignment may include splitting a received read and/or write I/O request at a first of a plurality of memory cache line boundaries to generate a first portion of the received I/O request. A second portion of the received read and/or write I/O request may be split into a plurality of segments so that each of the plurality of segments is aligned with one or more of the plurality of memory cache line boundaries. A cost of memory bandwidth for accessing host memory may be minimized based on the splitting of the second portion of the received read and/or write I/O request.

Abstract: Methods and systems for direct device access are disclosed. Aspects of one method may include a plurality of GOSs directly accessing a first network interface device, where the first network interface device may provide access to a network. One or more of the GOSs may be migrated to directly access a second network interface device, based on state information for each of the GOSs, where the state information may be maintained by the host. The GOSs may communicate data to a device coupled to the network by direct accessing the first and/or second network interface device. Similarly, the first and/or second network interface device may communicate data received from a device coupled to the network to one or more of the plurality of GOSs via direct access of the first and/or second network interface device.

Abstract: Certain aspects of a method and system for quality of service and congestion management for converged network interface devices are disclosed.