Patents by Inventor Kock Liang Heng

Kock Liang Heng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9054083
    Abstract: A semiconductor device includes a substrate and a via extending through the substrate. A first insulating layer is disposed on sidewalls of the via. An electrically conductive material is disposed in the via over the first insulating layer to form a TSV. A first interconnect structure is disposed over a first side of the substrate. A semiconductor die or a component is mounted to the first interconnect structure. An encapsulant is disposed over the first interconnect structure and semiconductor die or component. A second interconnect structure is disposed over the second side of the substrate. The second interconnect structure is electrically connected to the TSV. The second interconnect structure includes a second insulating layer disposed over the second surface of the substrate and TSV, and a first conductive layer disposed over the TSV and in contact with the TSV through the second insulating layer.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: June 9, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Nathapong Suthiwongsunthorn, Pandi C. Marimuthu, Jae Hun Ku, Glenn Omandam, Hin Hwa Goh, Kock Liang Heng, Jose A. Caparas
  • Patent number: 9029193
    Abstract: A semiconductor device has a first interconnect structure formed over a first side of a substrate. A semiconductor die is mounted to the first interconnect structure. An encapsulant is deposited over the semiconductor die and first interconnect structure for structural support. A portion of a second side of the substrate, opposite the first side of the substrate, is removed to reduce its thickness. The encapsulant maintains substrate robustness during thinning process. A TSV is formed through the second side of the substrate to the first interconnect structure. A second interconnect structure is formed in the TSV. The TSV has a first insulating layer formed over the second side of the substrate and first conductive layer formed over the first insulating layer and into the TSV. The second interconnect structure has a second conductive layer formed over the first conductive layer in an area away from the TSV.
    Type: Grant
    Filed: May 6, 2010
    Date of Patent: May 12, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Pandi Chelvam Marimuthu, Nathapong Suthiwongsunthorn, Kock Liang Heng
  • Publication number: 20140110861
    Abstract: A semiconductor device includes a substrate and a via extending through the substrate. A first insulating layer is disposed on sidewalls of the via. An electrically conductive material is disposed in the via over the first insulating layer to form a TSV. A first interconnect structure is disposed over a first side of the substrate. A semiconductor die or a component is mounted to the first interconnect structure. An encapsulant is disposed over the first interconnect structure and semiconductor die or component. A second interconnect structure is disposed over the second side of the substrate. The second interconnect structure is electrically connected to the TSV. The second interconnect structure includes a second insulating layer disposed over the second surface of the substrate and TSV, and a first conductive layer disposed over the TSV and in contact with the TSV through the second insulating layer.
    Type: Application
    Filed: December 30, 2013
    Publication date: April 24, 2014
    Applicant: STATS ChipPAC, Ltd.
    Inventors: Nathapong Suthiwongsunthorn, Pandi C. Marimuthu, Jae Hun Ku, Glenn Omandam, Hin Hwa Goh, Kock Liang Heng, Jose A. Caparas
  • Patent number: 8659162
    Abstract: A semiconductor device includes a substrate and a via extending through the substrate. A first insulating layer is disposed on sidewalls of the via. An electrically conductive material is disposed in the via over the first insulating layer to form a TSV. A first interconnect structure is disposed over a first side of the substrate. A semiconductor die or a component is mounted to the first interconnect structure. An encapsulant is disposed over the first interconnect structure and semiconductor die or component. A second interconnect structure is disposed over the second side of the substrate. The second interconnect structure is electrically connected to the TSV. The second interconnect structure includes a second insulating layer disposed over the second surface of the substrate and TSV, and a first conductive layer disposed over the TSV and in contact with the TSV through the second insulating layer.
    Type: Grant
    Filed: September 26, 2011
    Date of Patent: February 25, 2014
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Nathapong Suthiwongsunthorn, Pandi C. Marimuthu, Jae Hun Ku, Glenn Omandam, Hin Hwa Goh, Kock Liang Heng, Jose A. Caparas
  • Patent number: 8263439
    Abstract: A semiconductor device has a carrier for supporting the semiconductor device. A first semiconductor die is mounted over the carrier. A first dummy die having a first through-silicon via (TSV) is mounted over the carrier. The first semiconductor die and the first dummy die are encapsulated using a wafer molding material. The carrier is removed. A first redistribution layer (RDL) is formed over a first surface of the first semiconductor die and a first surface of the first dummy die to electrically connect the first TSV and a contact pad of the first semiconductor die. An insulation layer is formed over the first RDL. A second RDL is formed over a second surface of the first dummy die opposite the first surface of the first dummy die and electrically connected to the first TSV. A semiconductor package is connected to the second RDL.
    Type: Grant
    Filed: October 15, 2010
    Date of Patent: September 11, 2012
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Pandi Chelvam Marimuthu, Nathapong Suthiwongsunthorn, Il Kwon Shim, Kock Liang Heng
  • Patent number: 8125073
    Abstract: A semiconductor device has a wafer for supporting the device and a conductive layer formed over a top surface of the wafer. A carrier wafer is permanently bonded over the conductive layer. Within the wafer and the carrier wafer, an interconnect structure is formed. The interconnect structure includes a first via formed in the wafer that exposes the conductive layer, a second via formed in the carrier wafer that exposes the conductive layer, a first metal layer deposited over the first via, the first metal layer in electrical contact with the conductive layer, and a second metal layer deposited over the second via, the second metal layer in electrical contact with the conductive layer. First and second insulation layers are deposited over the first and second metal layers respectively. The first or second insulation layer has an etched portion to expose a portion of the first or second metal layer.
    Type: Grant
    Filed: January 11, 2011
    Date of Patent: February 28, 2012
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Byung Joon Han, Nathapong Suthiwongsunthorn, Pandi Chelvam Marimuthu, Kock Liang Heng
  • Publication number: 20120013004
    Abstract: A semiconductor device includes a substrate and a via extending through the substrate. A first insulating layer is disposed on sidewalls of the via. An electrically conductive material is disposed in the via over the first insulating layer to form a TSV. A first interconnect structure is disposed over a first side of the substrate. A semiconductor die or a component is mounted to the first interconnect structure. An encapsulant is disposed over the first interconnect structure and semiconductor die or component. A second interconnect structure is disposed over the second side of the substrate. The second interconnect structure is electrically connected to the TSV. The second interconnect structure includes a second insulating layer disposed over the second surface of the substrate and TSV, and a first conductive layer disposed over the TSV and in contact with the TSV through the second insulating layer.
    Type: Application
    Filed: September 26, 2011
    Publication date: January 19, 2012
    Applicant: STATS CHIPPAC, LTD.
    Inventors: Nathapong Suthiwongsunthorn, Pandi C. Marimuthu, Jae Hun Ku, Glenn Omandam, Hin Hwa Goh, Kock Liang Heng, Jose A. Caparas
  • Patent number: 8067308
    Abstract: A semiconductor device has a conductive via formed through in a first side of the substrate. A first interconnect structure is formed over the first side of the substrate. A semiconductor die or component is mounted to the first interconnect structure. An encapsulant is deposited over the first interconnect structure and semiconductor die or component. A portion of a second side of the substrate is removed to reduce its thickness and expose the TSV. A second interconnect structure is formed over the second side of the substrate. The encapsulant provides structural support while removing the portion of the second side of the substrate. The second interconnect structure is electrically connected to the conductive via. The second interconnect structure can include a redistribution layer to extend the conductivity of the conductive via. The semiconductor device is mounted to a printed circuit board through the second interconnect structure.
    Type: Grant
    Filed: June 8, 2009
    Date of Patent: November 29, 2011
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Nathapong Suthiwongsunthorn, Pandi C. Marimuthu, Jae Hun Ku, Glenn Omandam, Hin Hwa Goh, Kock Liang Heng, Jose A. Caparas
  • Patent number: 8049328
    Abstract: A semiconductor device has a first interconnect structure formed over a first side of a substrate. A semiconductor die is mounted to the first interconnect structure. An encapsulant is deposited over the semiconductor die and first interconnect structure for structural support. A portion of a second side of the substrate, opposite the first side of the substrate, is removed to reduce its thickness. The encapsulant maintains substrate robustness during thinning process. A TSV is formed through the second side of the substrate to the first interconnect structure. A second interconnect structure is formed in the TSV. The TSV has a first insulating layer formed over the second side of the substrate and first conductive layer formed over the first insulating layer and into the TSV. The second interconnect structure has a second conductive layer formed over the first conductive layer in an area away from the TSV.
    Type: Grant
    Filed: May 6, 2010
    Date of Patent: November 1, 2011
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Pandi C. Marimuthu, Nathapong Suthiwongsunthorn, Kock Liang Heng
  • Publication number: 20110101509
    Abstract: A semiconductor device has a wafer for supporting the device and a conductive layer formed over a top surface of the wafer. A carrier wafer is permanently bonded over the conductive layer. Within the wafer and the carrier wafer, an interconnect structure is formed. The interconnect structure includes a first via formed in the wafer that exposes the conductive layer, a second via formed in the carrier wafer that exposes the conductive layer, a first metal layer deposited over the first via, the first metal layer in electrical contact with the conductive layer, and a second metal layer deposited over the second via, the second metal layer in electrical contact with the conductive layer. First and second insulation layers are deposited over the first and second metal layers respectively. The first or second insulation layer has an etched portion to expose a portion of the first or second metal layer.
    Type: Application
    Filed: January 11, 2011
    Publication date: May 5, 2011
    Applicant: STATS CHIPPAC, LTD.
    Inventors: Byung Joon Han, Nathapong Suthiwongsunthorn, Pandi Chelvam Marimuthu, Kock Liang Heng
  • Publication number: 20110024916
    Abstract: A semiconductor device has a carrier for supporting the semiconductor device. A first semiconductor die is mounted over the carrier. A first dummy die having a first through-silicon via (TSV) is mounted over the carrier. The first semiconductor die and the first dummy die are encapsulated using a wafer molding material. The carrier is removed. A first redistribution layer (RDL) is formed over a first surface of the first semiconductor die and a first surface of the first dummy die to electrically connect the first TSV and a contact pad of the first semiconductor die. An insulation layer is formed over the first RDL. A second RDL is formed over a second surface of the first dummy die opposite the first surface of the first dummy die and electrically connected to the first TSV. A semiconductor package is connected to the second RDL.
    Type: Application
    Filed: October 15, 2010
    Publication date: February 3, 2011
    Applicant: STATS CHIPPAC, LTD.
    Inventors: Pandi Chelvam Marimuthu, Nathapong Suthiwongsunthorn, Il Kwon Shim, Kock Liang Heng
  • Patent number: 7880293
    Abstract: A semiconductor device has a wafer for supporting the device and a conductive layer formed over a top surface of the wafer. A carrier wafer is permanently bonded over the conductive layer. Within the wafer and the carrier wafer, an interconnect structure is formed. The interconnect structure includes a first via formed in the wafer exposing the conductive layer, a second via formed in the carrier wafer exposing the conductive layer, a first metal layer deposited over the first via, the first metal layer in electrical contact with the conductive layer, and a second metal layer deposited over the second via, the second metal layer in electrical contact with the conductive layer. First and second passivation layers are deposited over the first and second metal layers. The first or second passivation layer has an etched portion to expose a portion of the first metal layer or second metal layer.
    Type: Grant
    Filed: March 25, 2008
    Date of Patent: February 1, 2011
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Byung Joon Han, Nathapong Suthiwongsunthorn, Pandi Chelvam Marimuthu, Kock Liang Heng
  • Publication number: 20100308443
    Abstract: A semiconductor device has a conductive via formed through in a first side of the substrate. A first interconnect structure is formed over the first side of the substrate. A semiconductor die or component is mounted to the first interconnect structure. An encapsulant is deposited over the first interconnect structure and semiconductor die or component. A portion of a second side of the substrate is removed to reduce its thickness and expose the TSV. A second interconnect structure is formed over the second side of the substrate. The encapsulant provides structural support while removing the portion of the second side of the substrate. The second interconnect structure is electrically connected to the conductive via. The second interconnect structure can include a redistribution layer to extend the conductivity of the conductive via. The semiconductor device is mounted to a printed circuit board through the second interconnect structure.
    Type: Application
    Filed: June 8, 2009
    Publication date: December 9, 2010
    Applicant: STATS ChipPAC, Ltd.
    Inventors: Nathapong Suthiwongsunthorn, Pandi C. Marimuthu, Jae Hun Ku, Glenn Omandam, Hin Hwa Goh, Kock Liang Heng, Jose A. Caparas
  • Patent number: 7838337
    Abstract: A semiconductor device is fabricated by providing a carrier for supporting the semiconductor device. A first semiconductor die is mounted to the carrier. The first semiconductor die has a contact pad. A first dummy die is mounted to the carrier. The first dummy die has a through-silicon via (TSV). The first semiconductor die and the first dummy die are encapsulated using a wafer molding material. A first interconnect structure is formed over the first semiconductor die and the first dummy die. The first interconnect structure is connected to the contact pad of the first semiconductor die and the TSV of the first dummy die. The carrier is removed and a second interconnect structure is formed over the first semiconductor die and the first dummy die. The second interconnect structure is connected to the TSV of the first dummy die. A semiconductor package is connected to the second interconnect structure.
    Type: Grant
    Filed: December 1, 2008
    Date of Patent: November 23, 2010
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Pandi Chelvam Marimuthu, Nathapong Suthiwongsunthorn, Il Kwon Shim, Kock Liang Heng
  • Publication number: 20100221873
    Abstract: A semiconductor device has a first interconnect structure formed over a first side of a substrate. A semiconductor die is mounted to the first interconnect structure. An encapsulant is deposited over the semiconductor die and first interconnect structure for structural support. A portion of a second side of the substrate, opposite the first side of the substrate, is removed to reduce its thickness. The encapsulant maintains substrate robustness during thinning process. A TSV is formed through the second side of the substrate to the first interconnect structure. A second interconnect structure is formed in the TSV. The TSV has a first insulating layer formed over the second side of the substrate and first conductive layer formed over the first insulating layer and into the TSV. The second interconnect structure has a second conductive layer formed over the first conductive layer in an area away from the TSV.
    Type: Application
    Filed: May 6, 2010
    Publication date: September 2, 2010
    Applicant: STATS CHIPPAC, LTD.
    Inventors: Pandi Chelvam Marimuthu, Nathapong Suthiwongsunthorn, Kock Liang Heng
  • Publication number: 20100213610
    Abstract: A semiconductor device has a first interconnect structure formed over a first side of a substrate. A semiconductor die is mounted to the first interconnect structure. An encapsulant is deposited over the semiconductor die and first interconnect structure for structural support. A portion of a second side of the substrate, opposite the first side of the substrate, is removed to reduce its thickness. The encapsulant maintains substrate robustness during thinning process. A TSV is formed through the second side of the substrate to the first interconnect structure. A second interconnect structure is formed in the TSV. The TSV has a first insulating layer formed over the second side of the substrate and first conductive layer formed over the first insulating layer and into the TSV. The second interconnect structure has a second conductive layer formed over the first conductive layer in an area away from the TSV.
    Type: Application
    Filed: May 6, 2010
    Publication date: August 26, 2010
    Applicant: STATS CHIPPAC, LTD.
    Inventors: Pandi Chelvam Marimuthu, Nathapong Suthiwongsunthorn, Kock Liang Heng
  • Patent number: 7741148
    Abstract: A semiconductor device has a first interconnect structure formed over a first side of a substrate. A semiconductor die is mounted to the first interconnect structure. An encapsulant is deposited over the semiconductor die and first interconnect structure for structural support. A portion of a second side of the substrate, opposite the first side of the substrate, is removed to reduce its thickness. The encapsulant maintains substrate robustness during thinning process. A TSV is formed through the second side of the substrate to the first interconnect structure. A second interconnect structure is formed in the TSV. The TSV has a first insulating layer formed over the second side of the substrate and first conductive layer formed over the first insulating layer and into the TSV. The second interconnect structure has a second conductive layer formed over the first conductive layer in an area away from the TSV.
    Type: Grant
    Filed: December 10, 2008
    Date of Patent: June 22, 2010
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Pandi C. Marimuthu, Nathapong Suthiwongsunthorn, Kock Liang Heng
  • Publication number: 20100140815
    Abstract: A semiconductor device has a first interconnect structure formed over a first side of a substrate. A semiconductor die is mounted to the first interconnect structure. An encapsulant is deposited over the semiconductor die and first interconnect structure for structural support. A portion of a second side of the substrate, opposite the first side of the substrate, is removed to reduce its thickness. The encapsulant maintains substrate robustness during thinning process. A TSV is formed through the second side of the substrate to the first interconnect structure. A second interconnect structure is formed in the TSV. The TSV has a first insulating layer formed over the second side of the substrate and first conductive layer formed over the first insulating layer and into the TSV. The second interconnect structure has a second conductive layer formed over the first conductive layer in an area away from the TSV.
    Type: Application
    Filed: December 10, 2008
    Publication date: June 10, 2010
    Applicant: STATS ChipPAC, Ltd.
    Inventors: Pandi Chelvam Marimuthu, Nathapong Suthiwongsunthorn, Kock Liang Heng
  • Publication number: 20100133704
    Abstract: A semiconductor device is fabricated by providing a carrier for supporting the semiconductor device. A first semiconductor die is mounted to the carrier. The first semiconductor die has a contact pad. A first dummy die is mounted to the carrier. The first dummy die has a through-silicon via (TSV). The first semiconductor die and the first dummy die are encapsulated using a wafer molding material. A first interconnect structure is formed over the first semiconductor die and the first dummy die. The first interconnect structure is connected to the contact pad of the first semiconductor die and the TSV of the first dummy die. The carrier is removed and a second interconnect structure is formed over the first semiconductor die and the first dummy die. The second interconnect structure is connected to the TSV of the first dummy die. A semiconductor package is connected to the second interconnect structure.
    Type: Application
    Filed: December 1, 2008
    Publication date: June 3, 2010
    Applicant: STATS CHIPPAC, LTD.
    Inventors: Pandi Chelvam Marimuthu, Nathapong Suthiwongsunthorn, Il Kwon Shim, Kock Liang Heng
  • Publication number: 20090243083
    Abstract: A semiconductor device has a wafer for supporting the device and a conductive layer formed over a top surface of the wafer. A carrier wafer is permanently bonded over the conductive layer. Within the wafer and the carrier wafer, an interconnect structure is formed. The interconnect structure includes a first via formed in the wafer exposing the conductive layer, a second via formed in the carrier wafer exposing the conductive layer, a first metal layer deposited over the first via, the first metal layer in electrical contact with the conductive layer, and a second metal layer deposited over the second via, the second metal layer in electrical contact with the conductive layer. First and second passivation layers are deposited over the first and second metal layers. The first or second passivation layer has an etched portion to expose a portion of the first metal layer or second metal layer.
    Type: Application
    Filed: March 25, 2008
    Publication date: October 1, 2009
    Applicant: STATS CHIPPAC, LTD.
    Inventors: Byung Joon Han, Nathapong Suthiwongsunthorn, Pandi Chelvam Marimuthu, Kock Liang Heng