Abstract: An arithmetic processing unit includes a processing unit, a cache control unit that issues a request for the memory access, and a memory access controller that includes a request queue, and a request selection unit which selects a request from among requests enqueued in the request queue and issues the selected request to a memory. After issue of a previous request in the request queue, the request selection unit inhibits, during an issue inhibition period corresponding to the issued previous request, issue of a subsequent request corresponding to the issue inhibition period, and the request selection unit issues a second request in preference to a first request in a case where the requests in the request queue are in a first state, the first request being one of a read request and a write request in the request queue, and the second request being a request in the request queue.

Abstract: A memory controller that controls a plurality of memories individually through a communication route common to the plurality of memories, the memory controller including a holding unit that holds latency information, a storage that stores therein a request issued by a processor for a transmission destination memory from among the plurality of memories, an output unit that outputs the request from the storage, a transmitter that delays the request received from the output unit for a delay time based on a latency of the transmission destination memory and a latency of another memory from among the plurality of memories, and transmits the request to the transmission destination memory through the common communication route, and a data transceiver unit that transmits or receives data corresponding to the request through the common communication route after a prescribed time period has elapsed since the output unit output the request.

Abstract: Aspects may include a method of designing a system-on-chip. The method may include receiving multiple processing modules, each representing in software one of multiple processing units of a system-on-chip. The method may further include modeling communications from one or more of the multiple processing modules as accesses to memory. The method may further include generating a coherent memory module associated with the multiple processing modules based on modeling the communications from the one or more of the multiple processing modules as accesses to memory. The coherent memory module may represent in software a coherent memory associated with the multiple processing units.

Abstract: Aspects may include a method of designing a system-on-chip. The method may include receiving multiple processing modules, each representing in software one of multiple processing units of a system-on-chip. The method may further include modeling communications from one or more of the multiple processing modules as accesses to memory. The method may further include generating a coherent memory module associated with the multiple processing modules based on modeling the communications from the one or more of the multiple processing modules as accesses to memory. The coherent memory module may represent in software a coherent memory associated with the multiple processing units.

Abstract: Aspects may include a method of designing a system-on-chip. The method may include receiving multiple processing modules, each representing in software one of multiple processing units of a system-on-chip. The method may further include modeling communications from one or more of the multiple processing modules as accesses to memory. The method may further include generating a coherent memory module associated with the multiple processing modules based on modeling the communications from the one or more of the multiple processing modules as accesses to memory. The coherent memory module may represent in software a coherent memory associated with the multiple processing units.

Abstract: Aspects may include a method of designing a system-on-chip. The method may include receiving multiple processing modules, each representing in software one of multiple processing units of a system-on-chip. The method may further include modeling communications from one or more of the multiple processing modules as accesses to memory. The method may further include generating a coherent memory module associated with the multiple processing modules based on modeling the communications from the one or more of the multiple processing modules as accesses to memory. The coherent memory module may represent in software a coherent memory associated with the multiple processing units.