Patents by Inventor Kodai Murata

Kodai Murata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11820118
    Abstract: A lamination device that laminates a plurality of types of workpieces includes a plurality of supply mechanisms that supply a workpiece to each of a plurality of supply positions, a movement mechanism including a stator of a linear motor having a predetermined traveling track and a mover of a linear motor that is movable between a plurality of the supply positions along a traveling track, and a control unit that controls at least the mover. The mover includes a lamination stage for laminating the workpiece. The control unit corrects a relative position of the workpiece supplied to the supply positions with respect to the lamination stage, laminates the workpiece whose relative position is corrected on the lamination stage, and controls the mover so as to move to a next one of the supply positions after lamination of the workpiece.
    Type: Grant
    Filed: October 28, 2022
    Date of Patent: November 21, 2023
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Arata Suzuki, Kouhei Fukuda, Kodai Murata
  • Publication number: 20230080579
    Abstract: A lamination device that laminates a plurality of types of workpieces includes supply mechanisms that supply the workpiece to each of supply positions, a movement mechanism including a stator of a linear motor having a predetermined traveling track and a mover of a linear motor that is movable between a plurality of the supply positions along a traveling track, and a controller that controls at least the mover. The mover includes a holding unit that holds the workpiece supplied to the supply positions, and a lamination stage for lamination the workpiece. The controller corrects a relative position of the workpiece with respect to the lamination stage and controls the mover to laminate the workpiece whose relative position is corrected on the lamination stage while the holding unit holds the workpiece supplied to the supply positions and moves to and stops at a next one of the supply positions.
    Type: Application
    Filed: October 28, 2022
    Publication date: March 16, 2023
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Arata SUZUKI, Kouhei FUKUDA, Kodai MURATA
  • Publication number: 20230072704
    Abstract: A lamination device that laminates a plurality of types of workpieces includes a plurality of supply mechanisms that supply a workpiece to each of a plurality of supply positions, a movement mechanism including a stator of a linear motor having a predetermined traveling track and a mover of a linear motor that is movable between a plurality of the supply positions along a traveling track, and a control unit that controls at least the mover. The mover includes a lamination stage for laminating the workpiece. The control unit corrects a relative position of the workpiece supplied to the supply positions with respect to the lamination stage, laminates the workpiece whose relative position is corrected on the lamination stage, and controls the mover so as to move to a next one of the supply positions after lamination of the workpiece.
    Type: Application
    Filed: October 28, 2022
    Publication date: March 9, 2023
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Arata SUZUKI, Kouhei FUKUDA, Kodai MURATA
  • Patent number: 9472673
    Abstract: A source electrode (5) and a drain electrode (6) are film-formed, and a semiconductor layer (7) is formed in a substantially stripe shape substantially parallel to the X axis direction (channel-length direction) using a coating method. Then, a protection layer (8) is formed in a substantially stripe shape substantially parallel to the Y axis direction (channel width direction) orthogonal to the semiconductor layer (7). Then, a semiconductor layer (7) portion not covered with the protection layer (8) is removed using an organic solvent or an inorganic solvent or a mixed solution of the organic solvent and the inorganic solvent. Consequently, the semiconductor layer (7) and the protection layer (8) are formed with improved alignment accuracy, and electrical isolation between transistor elements (50) can be achieved with a simplified process.
    Type: Grant
    Filed: January 26, 2015
    Date of Patent: October 18, 2016
    Assignee: TOPPAN PRINTING CO., LTD.
    Inventor: Kodai Murata
  • Publication number: 20150129862
    Abstract: A source electrode (5) and a drain electrode (6) are film-formed, and a semiconductor layer (7) is formed in a substantially stripe shape substantially parallel to the X axis direction (channel-length direction) using a coating method. Then, a protection layer (8) is formed in a substantially stripe shape substantially parallel to the Y axis direction (channel width direction) orthogonal to the semiconductor layer (7). Then, a semiconductor layer (7) portion not covered with the protection layer (8) is removed using an organic solvent or an inorganic solvent or a mixed solution of the organic solvent and the inorganic solvent. Consequently, the semiconductor layer (7) and the protection layer (8) are formed with improved alignment accuracy, and electrical isolation between transistor elements (50) can be achieved with a simplified process.
    Type: Application
    Filed: January 26, 2015
    Publication date: May 14, 2015
    Inventor: Kodai MURATA
  • Patent number: 8963141
    Abstract: A method for fabricating a thin-film transistor is provided whereby isolation of transistor devices is realized and the performance and the stability of the product thin-film transistor are improved. The thin-film transistor includes a substrate; a gate electrode laminated on the substrate; a gate insulating layer laminated on the substrate and the gate electrode; a recessed portion provided in the gate insulating layer; a semiconductor layer formed in the recessed portion of the gate insulating layer; and a source electrode and a drain electrode connected to the semiconductor layer at respective positions which are spaced apart from each other.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: February 24, 2015
    Assignee: Toppan Printing Co., Ltd.
    Inventor: Kodai Murata
  • Patent number: 8487308
    Abstract: One embodiment of the present invention is a thin film transistor having a substrate, a gate electrode formed on the substrate, a gate insulating film, a semiconductor layer formed on the gate insulating film, a protective film formed on the semiconductor layer and the gate insulating film and having first and second opening sections which are separately and directly formed on the semiconductor layer, a source electrode formed on the protective film and electrically connected to the semiconductor layer at the first opening section of the protective film, and a drain electrode formed on the protective film and electrically connected to the semiconductor layer at the second opening section of the protective film.
    Type: Grant
    Filed: April 2, 2010
    Date of Patent: July 16, 2013
    Assignee: Toppan Printing Co., Ltd.
    Inventors: Noriaki Ikeda, Kodai Murata, Manabu Ito, Chihiro Miyazaki
  • Publication number: 20100258805
    Abstract: One embodiment of the present invention is a thin film transistor having a substrate, a gate electrode formed on the substrate, a gate insulating film, a semiconductor layer formed on the gate insulating film, a protective film formed on the semiconductor layer and the gate insulating film and having first and second opening sections which are separately and directly formed on the semiconductor layer, a source electrode formed on the protective film and electrically connected to the semiconductor layer at the first opening section of the protective film, and a drain electrode formed on the protective film and electrically connected to the semiconductor layer at the second opening section of the protective film.
    Type: Application
    Filed: April 2, 2010
    Publication date: October 14, 2010
    Applicant: Toppan Printing Co., Ltd.
    Inventors: Noriaki Ikeda, Kodai Murata, Manabu Ito, Chihiro Miyazaki