Patents by Inventor Kodai Wada

Kodai Wada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240162222
    Abstract: Reliability of a semiconductor device is improved and reduction in yield is reduced. In a semiconductor substrate SUB, a trench TR is formed. A gate-electrode GE1 is formed inside the trench TR via a gate insulating film GI1. In the semiconductor substrate SUB, a body region PB, a well region PW1 and a well region NW1 are formed. A source-region NS is formed in the body-region PB. In the well region PW1, an n-type source region and an n-type drain region are formed. In the well region NW1, a p-type source region and a p-type drain region are formed. The source region NS, the n-type source region, the n-type drain region, the p-type source region and the p-type drain region are subjected to heat treatment. After heat treatment, a p-type column region PC is formed in the semiconductor substrate SUB located below the body region PB.
    Type: Application
    Filed: November 15, 2023
    Publication date: May 16, 2024
    Inventors: Hiroshi YANAGIGAWA, Hideki NIWAYAMA, Hiroyoshi KUDOU, Kazuhisa MORI, Kodai WADA
  • Publication number: 20240162143
    Abstract: In a semiconductor substrate SUB, a trench TR is formed. A gate-electrode GE1 is formed inside the trench TR via a gate insulating film GI1. A body region PB, a well region PW1 and a well region NW1 are formed. A source-region NS is formed in the body-region PB. In the well region PW1, an n-type source region and an n-type drain region are formed. In the well region NW1, a p-type source region and a p-type drain region are formed. An interlayer insulating film IL1 is formed on the upper surface of semiconductor substrate SUB. In the interlayer insulating film IL1, a hole CH1 is formed in the source region NS and in the body region PB. Holes CH3 are formed in the interlayer insulating film IL1 so as to reach the n-type source region, the n-type drain region, the p-type source region and the p-type drain region.
    Type: Application
    Filed: November 15, 2023
    Publication date: May 16, 2024
    Inventors: Hiroshi YANAGIGAWA, Hideki NIWAYAMA, Hiroyoshi KUDOU, Kazuhisa MORI, Kodai WADA
  • Patent number: 11471770
    Abstract: A game server 30 includes: a processing unit 38 that deletes an item obtained by a user and increases the value of a parameter on the basis of an experience value of the deleted item when a condition preset by the user is satisfied; an item box 35 that stores the item obtained by the user when the condition is not satisfied; and a present box 36 that stores the item obtained by the user when the condition is not satisfied and the number of items stored in the item box 35 has reached an upper-limit value.
    Type: Grant
    Filed: January 22, 2021
    Date of Patent: October 18, 2022
    Assignee: CYGAMES, INC.
    Inventors: Kodai Wada, Kunihiko Matsuda, Satoshi Hiroshima
  • Publication number: 20210138346
    Abstract: A game server 30 includes: a processing unit 38 that deletes an item obtained by a user and increases the value of a parameter on the basis of an experience value of the deleted item when a condition preset by the user is satisfied; an item box 35 that stores the item obtained by the user when the condition is not satisfied; and a present box 36 that stores the item obtained by the user when the condition is not satisfied and the number of items stored in the item box 35 has reached an upper-limit value.
    Type: Application
    Filed: January 22, 2021
    Publication date: May 13, 2021
    Applicant: CYGAMES, INC.
    Inventors: Kodai Wada, Kunihiko Matsuda, Satoshi Hiroshima