Abstract: The present invention relates to a method of detecting an anomaly using a plurality of images. The method comprises determining a subset of images from the plurality of images, comprising one or more first features. Further, one or more regions comprising one or more second features are identified in each image from the subset of images. Finally, detecting the anomaly from the subset of images based on the one or more regions. Therefore, accuracy of detecting anomalies is increased by using the subset of images.

Abstract: A method and system for rendering object detection graphics on image frames is disclosed. The method includes receiving an object detection information for an image frame. The object detection information includes bounding box data and a class label data associated with an object in the image frame. The method further includes determining a first value for each pixel in a first set of pixels associated with a bounding box for the object and determining a second value for each pixel in a second set of pixels associated with a class label for the object. The method includes modifying values for each of the first set of pixels based on the associated first value to render the bounding box on the image frame and modifying values for each of the second set of pixels based on the associated second value to render the class label on the image frame.

Abstract: The present invention relates to a method of detecting an anomaly using a plurality of images. The method comprises determining a subset of images from the plurality of images, comprising one or more first features. Further, one or more regions comprising one or more second features are identified in each image from the subset of images. Finally, detecting the anomaly from the subset of images based on the one or more regions. Therefore, accuracy of detecting anomalies is increased by using the subset of images.

Abstract: A method and system for rendering object detection graphics on image frames is disclosed. The method includes receiving an object detection information for an image frame. The object detection information includes bounding box data and a class label data associated with an object in the image frame. The method further includes determining a first value for each pixel in a first set of pixels associated with a bounding box for the object and determining a second value for each pixel in a second set of pixels associated with a class label for the object. The method includes modifying values for each of the first set of pixels based on the associated first value to render the bounding box on the image frame and modifying values for each of the second set of pixels based on the associated second value to render the class label on the image frame.

Abstract: Embodiments of present disclosure relates to a method and a system for implementation of user logic in a FPGA device. For the implementation, user logic is mapped onto cells of the FPGA device in implementation platform associated with FPGA device. The mapping is based on user logic constraints to be met and received for FPGA device. Further, mapped cells of FPGA device are placed in implementation platform based on local mapping optimization parameters. The placing also comprises of performing placement optimization on placed cells of FPGA device. Upon placement, placed cells of FPGA device are routed in implementation platform based on at least local mapping optimization parameters and local placement optimization parameters. The routing also comprises of performing routing optimization on routed cells of FPGA device.

Abstract: This disclosure relates generally to distributed video coding. In one embodiment, distributed video encoding apparatus to achieve improved rate distortion performance is disclosed. The distributed video encoding apparatus comprises a processor and a memory communicatively coupled to the processor. The memory stores processor instructions, which, on execution, causes the processor to receive at least one Group of Pictures (GOP) comprising at least one key frame and at least one Wyner-Ziv (WZ) frame. The processor further determines a first value that is indicative of a cumulative motion activity associated with the at least one GOP. The processor further classifies the at least one GOP into one of one or more high-motion WZ frames and one or more low-motion WZ frames based on the determined first value. The processor encodes the high-motion WZ frames using inter no-motion encoding. The processor further encodes the one or more low-motion WZ frames using Wyner-Ziv encoding.

Abstract: Embodiments of the present disclosure relates to a method and a system for switching display from a first video source to a second video source. The system receives a source switch indication request for switching the display from the first video source to the second video source identified by source identification of the second video source. Further the system synchronizes the source switch indication request using frame sync of the first video source and the second video sources and mask the interface signals of the first video source to generate output interface signals corresponding to the second video source. The display is then driven by the output interface signals of the second video source thereby enabling seamless switching of the display without using frame buffer, thereby rendering the video stream from multiple video sources without any tearing artifacts or display glitches and still optimizing the switching latency.

Abstract: Embodiments of present disclosure relates to a method and a system for implementation of user logic in a FPGA device. For the implementation, user logic is mapped onto cells of the FPGA device in implementation platform associated with FPGA device. The mapping is based on user logic constraints to be met and received for FPGA device. Further, mapped cells of FPGA device are placed in implementation platform based on local mapping optimization parameters. The placing also comprises of performing placement optimization on placed cells of FPGA device. Upon placement, placed cells of FPGA device are routed in implementation platform based on at least local mapping optimization parameters and local placement optimization parameters. The routing also comprises of performing routing optimization on routed cells of FPGA device.

Abstract: Embodiments of the present disclosure relates to a method and a system for switching display from a first video source to a second video source. The system receives a source switch indication request for switching the display from the first video source to the second video source identified by source identification of the second video source. Further the system synchronizes the source switch indication request using frame sync of the first video source and the second video sources and mask the interface signals of the first video source to generate output interface signals corresponding to the second video source. The display is then driven by the output interface signals of the second video source thereby enabling seamless switching of the display without using frame buffer, thereby rendering the video stream from multiple video sources without any tearing artifacts or display glitches and still optimizing the switching latency.

Abstract: A method of mapping target design memory blocks to embedded memory blocks in a semiconductor device of an embedded system is disclosed. The method includes categorizing a plurality target design memory blocks based on memory operation patterns into one of an overlapping category and a non-overlapping category; identifying a set of target design memory blocks that satisfy capacity criteria of a single embedded memory block in the semiconductor device, each target design memory block in the set is identified from either the overlapping category or the non-overlapping category; designing semiconductor device components to be created on the semiconductor device based on one of the overlapping category and the non-overlapping category, which the set of target design memory blocks is associated with; implementing the set of target design memory blocks and the semiconductor device components onto the single embedded memory block of the semiconductor device.

Abstract: Method and a computing device for providing privacy control in a surveillance video is disclosed. The computing device receives a surveillance video from a video capturing. The computing device also receives an authentication input key from a user of the computing device. Based on the authentication input key, the computing device identifies one or more region of interests (ROIs) in the video surveillance. The identified ROIs are masked by the computing device for providing the privacy control. In the present disclosure, the number of privacy levels achievable are unlimited and not fixed by ROIs at the video capturing device end. The increase in number of privacy levels do not require any changes or complexity/power increase in the video capturing device end and doesn't demand for increase in bandwidth from the video capturing device. Further, it doesn't deteriorate the video quality.

Abstract: Method and a computing device for providing privacy control in a surveillance video is disclosed. The computing device receives a surveillance video from a video capturing. The computing device also receives an authentication input key from a user of the computing device. Based on the authentication input key, the computing device identifies one or more region of interests (ROIs) in the video surveillance. The identified ROIs are masked by the computing device for providing the privacy control. In the present disclosure, the number of privacy levels achievable are unlimited and not fixed by ROIs at the video capturing device end. The increase in number of privacy levels do not require any changes or complexity/power increase in the video capturing device end and doesn't demand for increase in bandwidth from the video capturing device. Further, it doesn't deteriorate the video quality.

Abstract: This disclosure relates generally to data processing, and more particularly, to methods and systems for memory initialization of an integrated circuit. In one embodiment, a method for memory initialization at a circuitry is provided. The method comprises: identifying a portion of the circuitry configured as a memory device; detecting a start of a power-off state for a power domain within the circuitry including the memory device; performing a write operation to write data of a pre-determined pattern to the memory device upon detecting the start of the power-off state; and providing the data stored at the memory device for a reading operation after the power-off state ends.

Abstract: A method of mapping target design memory blocks to embedded memory blocks in a semiconductor device of an embedded system is disclosed. The method includes categorizing a plurality target design memory blocks based on memory operation patterns into one of an overlapping category and a non-overlapping category; identifying a set of target design memory blocks that satisfy capacity criteria of a single embedded memory block in the semiconductor device, each target design memory block in the set is identified from either the overlapping category or the non-overlapping category; designing semiconductor device components to be created on the semiconductor device based on one of the overlapping category and the non-overlapping category, which the set of target design memory blocks is associated with; implementing the set of target design memory blocks and the semiconductor device components onto the single embedded memory block of the semiconductor device.

Abstract: This disclosure relates generally to distributed video coding. In one embodiment, distributed video encoding apparatus to achieve improved rate distortion performance is disclosed. The distributed video encoding apparatus comprises a processor and a memory communicatively coupled to the processor. The memory stores processor instructions, which, on execution, causes the processor to receive at least one Group of Pictures (GOP) comprising at least one key frame and at least one Wyner-Ziv (WZ) frame. The processor further determines a first value that is indicative of a cumulative motion activity associated with the at least one GOP. The processor further classifies the at least one GOP into one of one or more high-motion WZ frames and one or more low-motion WZ frames based on the determined first value. The processor encodes the high-motion WZ frames using inter no-motion encoding. The processor further encodes the one or more low-motion WZ frames using Wyner-Ziv encoding.

Abstract: This disclosure relates generally to data processing, and more particularly, to methods and systems for memory initialization of an integrated circuit. In one embodiment, a method for memory initialization at a circuitry is provided. The method comprises: identifying a portion of the circuitry configured as a memory device; detecting a start of a power-off state for a power domain within the circuitry including the memory device; performing a write operation to write data of a pre-determined pattern to the memory device upon detecting the start of the power-off state; and providing the data stored at the memory device for a reading operation after the power-off state ends.

Abstract: This technology relates generally to integrated circuit technologies, and more particularly, to methods and systems for configuring a field programmable device. In one embodiment, a method for configuring a field programmable device is provided. The method comprises: identifying information associated with a plurality of logic functions associated with a plurality of subsystems to be implemented on a field programmable device; determining, based on the information, a set of attributes associated with each of the plurality of subsystems; determining, based on the set of attributes, a first value indicative of an estimation of a total number of the sequential logic blocks, and a second value indicative of an estimation of a total number of the combinational logic blocks, for implementing the plurality of logic functions; determining, based on the first and second values, to configure a first field programmable device for implementing the plurality of logic functions.