Patents by Inventor Koe Sun Pak

Koe Sun Pak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Low cost high performance EEPROM device
    Patent number: 9806087
    Abstract: Devices and methods for forming a device are presented. The method includes providing a substrate prepared with a cell area separated by other active areas by isolation regions. First and second lower sub-gates of first and second transistors are formed in the cell area. A common upper sub-gate of the first and second transistors is formed. The common upper sub-gate and first and second lower sub-gates are separated by an intergate dielectric layer and the common upper sub-gate surrounds the first and second lower sub-gates.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: October 31, 2017
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Chandrasekar Venkataramani, Qiuji Zhao, Koe Sun Pak, Bai Yen Nguyen, Yoke Weng Tam
  • LOW COST HIGH PERFORMANCE EEPROM DEVICE
    Publication number: 20170263617
    Abstract: Devices and methods for forming a device are presented. The method includes providing a substrate prepared with a cell area separated by other active areas by isolation regions. First and second lower sub-gates of first and second transistors are formed in the cell area. A common upper sub-gate of the first and second transistors is formed. The common upper sub-gate and first and second lower sub-gates are separated by an intergate dielectric layer and the common upper sub-gate surrounds the first and second lower sub-gates.
    Type: Application
    Filed: May 22, 2017
    Publication date: September 14, 2017
    Inventors: Chandrasekar VENKATARAMANI, Qiuji ZHAO, Koe Sun PAK, Bai Yen NGUYEN, Yoke Weng TAM
  • Low cost high performance EEPROM device
    Patent number: 9659947
    Abstract: Devices and methods for forming a device are presented. The method includes providing a substrate prepared with a cell area separated by other active areas by isolation regions. First and second lower sub-gates of first and second transistors are formed in the cell area. A common upper sub-gate of the first and second transistors is formed. The common upper sub-gate and first and second lower sub-gates are separated by an intergate dielectric layer and the common upper sub-gate surrounds the first and second lower sub-gates.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: May 23, 2017
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Chandrasekar Venkataramani, Qiuji Zhao, Koe Sun Pak, Bai Yen Nguyen, Yoke Weng Tam