Patents by Inventor Koen R. C. Bennebroek

Koen R. C. Bennebroek has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • N-way set-associative external cache with standard DDR memory devices
    Patent number: 6912628
    Abstract: A method, cache system, and cache controller are provided. A two-way and n-way cache organization scheme are presented as at least two embodiments of a set-associative external cache that utilizes standard burst memory devices such as DDR (double data rate) memory devices. The set-associative cache organization scheme is designed to fully utilize burst efficiencies during snoop and invalidation operations. Cache lines are interleaved in such a way that a first burst transfer from the cache to the cache controller brings in a plurality of tags.
    Type: Grant
    Filed: April 22, 2002
    Date of Patent: June 28, 2005
    Assignee: Sun Microsystems Inc.
    Inventors: Thomas M. Wicki, Koen R. C. Bennebroek
  • Interleaved n-way set-associative external cache
    Patent number: 6832294
    Abstract: An n-way interleaved set-associative external cache utilizes standard burst memory devices such as DDR (double data rate) memory devices. The interleaved set-associative cache organization scheme is designed to fully utilize burst efficiencies during snoop and invalidation operations. Cache lines are interleaved in such a way that a first burst transfer from the cache to the cache controller brings in a plurality of tags. The contents of the memory level device locations associated with each tag are stored in an alternating pattern in contiguous memory locations.
    Type: Grant
    Filed: April 22, 2002
    Date of Patent: December 14, 2004
    Assignee: Sun Microsystems, Inc.
    Inventors: Thomas M. Wicki, Koen R. C. Bennebroek
  • N-way set-associative external cache with standard DDR memory devices
    Publication number: 20030200404
    Abstract: A method, cache system, and cache controller are provided. A two-way and n-way cache organization scheme are presented as at least two embodiments of a set-associative external cache that utilizes standard burst memory devices such as DDR (double data rate) memory devices. The set-associative cache organization scheme is designed to fully utilize burst efficiencies during snoop and invalidation operations. Cache lines are interleaved in such a way that a first burst transfer from the cache to the cache controller brings in a plurality of tags.
    Type: Application
    Filed: April 22, 2002
    Publication date: October 23, 2003
    Inventors: Thomas M. Wicki, Koen R.C. Bennebroek
  • Interleaved n-way set-associative external cache
    Publication number: 20030200395
    Abstract: An n-way interleaved set-associative external cache utilizes standard burst memory devices such as DDR (double data rate) memory devices. The interleaved set-associative cache organization scheme is designed to fully utilize burst efficiencies during snoop and invalidation operations. Cache lines are interleaved in such a way that a first burst transfer from the cache to the cache controller brings in a plurality of tags. The contents of the memory level device locations associated with each tag are stored in an alternating pattern in contiguous memory locations.
    Type: Application
    Filed: April 22, 2002
    Publication date: October 23, 2003
    Inventors: Thomas M. Wicki, Koen R.C. Bennebroek