Patents by Inventor Koenraad F. Van Schuylenbergh

Koenraad F. Van Schuylenbergh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6848175
    Abstract: Several methods and structures for improving the yield of out-of-plane micro-device structures including springs and coils are described. In one method the springs used to form out-of-plane structures are constrained via a tether to avoid bunching and entanglement. The high yield structure may be used in numerous electronic applications such as filter circuits.
    Type: Grant
    Filed: April 16, 2003
    Date of Patent: February 1, 2005
    Assignee: Xerox Corporation
    Inventors: David K. Fork, Ping Mei, Koenraad F. Van Schuylenbergh
  • Patent number: 6720594
    Abstract: Improved pixel circuits are disclosed for high fill-factor large area imager systems using continuous (e.g., amorphous silicon) sensor layers. A first approach prevents crosstalk by ensuring that each pixel is not able to go into saturation. A second approach employs a cascode transistor to maintain the bias of the sensor contact at a constant potential regardless of illumination condition. These two approaches may be combined. A resistive film connecting the pixel contacts may be used in conjunction with the second approach to prevent aliasing of signal and noise.
    Type: Grant
    Filed: January 7, 2002
    Date of Patent: April 13, 2004
    Assignee: Xerox Corporation
    Inventors: Jeffrey T. Rahn, Koenraad F. Van Schuylenbergh, Jeng Ping Lu
  • Publication number: 20040017494
    Abstract: An imager circuit includes an array of pixels, each pixel including a sensor (photodiode) connected to an input terminal of a comparator. The comparators of each pixel row have output terminals connected to a latch. A counter generates a sequence of digital values that are transmitted to a digital-to-analog converter (DAC) and to the latch of each row. The DAC generates a ramp voltage that is transmitted to a second input terminal of each pixel's comparator. The comparators of a selected pixel column are enabled to generate output signals when the ramp voltage equals each pixel's voltage, causing the associated latches to capture the current digital values. The comparators are formed such that each pixel row shares a cascode mirror circuit that detects differential currents in data line pairs connected to each pixel in that row.
    Type: Application
    Filed: July 26, 2002
    Publication date: January 29, 2004
    Applicant: Xerox Corporation
    Inventors: Jeng Ping Lu, Koenraad F. Van Schuylenbergh
  • Patent number: 6655964
    Abstract: Several methods and structures for improving the yield of out-of-plane micro-device structures including springs and coils are described. In one method the elastic members have graded perforations for controlling rate of release. In another method and structure, a layout enables the contact landing area to be increased. The high yield structures may be used in numerous electronic applications such as filter circuits.
    Type: Grant
    Filed: February 9, 2001
    Date of Patent: December 2, 2003
    Assignee: Xerox Corporation
    Inventors: David K. Fork, Christopher L. Chua, Koenraad F. Van Schuylenbergh, Noble M. Johnson, David K. Biegelsen
  • Publication number: 20030211761
    Abstract: Several methods and structures for improving the yield of out-of-plane micro-device structures including springs and coils are described. In one method the springs used to form out-of-plane structures are constrained via a tether to avoid bunching and entanglement. The high yield structure may be used in numerous electronic applications such as filter circuits.
    Type: Application
    Filed: April 16, 2003
    Publication date: November 13, 2003
    Applicant: Xerox Corporation
    Inventors: David K. Fork, Ping Mei, Koenraad F. Van Schuylenbergh
  • Publication number: 20030179064
    Abstract: An out-of-plane micro-structure which can be used for on-chip integration of high-Q inductors and transformers places the magnetic field direction parallel to the substrate plane without requiring high aspect ratio processing. The photolithographically patterned coil structure includes an elastic member having an intrinsic stress profile. The intrinsic stress profile biases a free portion away from the substrate forming a loop winding. An anchor portion remains fixed to the substrate. The free portion end becomes a second anchor portion which may be connected to the substrate via soldering or plating. A series of individual coil structures can be joined via their anchor portions to form inductors and transformers.
    Type: Application
    Filed: March 11, 2003
    Publication date: September 25, 2003
    Applicant: Xerox Corporation
    Inventors: Christopher L. Chua, Francesco Lemmi, Koenraad F. Van Schuylenbergh, Jeng Ping Lu, David K. Fork, Eric Peeters, Decai Sun, Donald L. Smith, Linda T. Romano
  • Patent number: 6621141
    Abstract: Patterned ground planes are formed between out-of-plane microcoil structures and underlying integrated circuits (ICs). Each out-of-plane coil includes a series of loops extending from base (contact) pads formed on a dielectric layer (e.g., thick IC passivation, or BCB formed on thin passivation). Losses due to capacitive coil-to-substrate coupling are minimized using a central ground plane structure located under the base pads of the microcoil. Magnetic losses are reduced by forming a low-resistance ground plane structure including end portions located outside of the ends of the microcoil. The low-resistance ground plane can be slotted to reduce the loop size of eddy current pathways. The low-resistance ground plane is formed from one or more of the top IC metal layers, copper pads formed between the IC passivation and the dielectric, portions of the metal used to form the microcoil, or combinations thereof.
    Type: Grant
    Filed: July 22, 2002
    Date of Patent: September 16, 2003
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Koenraad F. Van Schuylenbergh, Christopher L. Chua, David K. Fork
  • Patent number: 6606235
    Abstract: A new type of high-Q variable capacitor includes a substrate, a first electrically conductive layer fixed to the substrate, a dielectric layer fixed to a portion of the electrically conductive layer, and a second electrically conductive layer having an anchor portion and a free portion. The anchor portion is fixed to the dielectric layer and the free portion is initially fixed to the dielectric layer, but is released from the dielectric layer to become separated from the dielectric layer, and wherein an inherent stress profile in the second electrically conductive layer biases the free portion away from the a dielectric layer. When a bias voltage is applied between the first electrically conductive layer and the second electrically conductive layer, electrostatic forces in the free portion bend the free portion towards the first electrically conductive layer, thereby increasing the capacitance of the capacitor.
    Type: Grant
    Filed: May 23, 2002
    Date of Patent: August 12, 2003
    Inventors: Christopher L. Chua, Eric Peeters, Koenraad F. Van Schuylenbergh, Donald L. Smith
  • Patent number: 6595787
    Abstract: Several methods and structures for improving the yield of out-of-plane micro-device structures including springs and coils are described. In one method the springs used to form out-of-plane structures are constrained via a tether to avoid bunching and entanglement. The high yield structure may be used in numerous electronic applications such as filter circuits.
    Type: Grant
    Filed: February 9, 2001
    Date of Patent: July 22, 2003
    Assignee: Xerox Corporation
    Inventors: David K. Fork, Ping Mei, Koenraad F. Van Schuylenbergh
  • Publication number: 20030127672
    Abstract: Improved pixel circuits are disclosed for high fill-factor large area imager systems using continuous (e.g., amorphous silicon) sensor layers. A first approach prevents crosstalk by ensuring that each pixel is not able to go into saturation. A second approach employs a cascode transistor to maintain the bias of the sensor contact at a constant potential regardless of illumination condition. These two approaches may be combined. A resistive film connecting the pixel contacts may be used in conjunction with the second approach to prevent aliasing of signal and noise.
    Type: Application
    Filed: January 7, 2002
    Publication date: July 10, 2003
    Inventors: Jeffrey T. Rahn, Koenraad F. Van Schuylenbergh, Jeng Ping Lu
  • Publication number: 20030115086
    Abstract: The present invention relates to a method for controlling non-linear coupled systems with a single output. More particularly, the present invention relates to control and coordination of force actuators that act on a single object without use of a central controller.
    Type: Application
    Filed: September 24, 1999
    Publication date: June 19, 2003
    Inventors: WARREN B. JACKSON, DAVID K. BIEGELSEN, TAD H. HOGG, CHEE WE NG, ANDREW A. BERLIN, KOENRAAD F. VAN SCHUYLENBERGH, CARLOS MOCHON
  • Publication number: 20030030965
    Abstract: A new type of high-Q variable capacitor includes a substrate, a first electrically conductive layer fixed to the substrate, a dielectric layer fixed to a portion of the electrically conductive layer, and a second electrically conductive layer having an anchor portion and a free portion. The anchor portion is fixed to the dielectric layer and the free portion is initially fixed to the dielectric layer, but is released from the dielectric layer to become separated from the dielectric layer, and wherein an inherent stress profile in the second electrically conductive layer biases the free portion away from the a dielectric layer. When a bias voltage is applied between the first electrically conductive layer and the second electrically conductive layer, electrostatic forces in the free portion bend the free portion towards the first electrically conductive layer, thereby increasing the capacitance of the capacitor.
    Type: Application
    Filed: May 23, 2002
    Publication date: February 13, 2003
    Applicant: Xerox Corporation
    Inventors: Christopher L. Chua, Eric Peeters, Koenraad F. Van Schuylenbergh, Donald L. Smith
  • Publication number: 20030027081
    Abstract: An out-of-plane micro-structure which can be used for on-chip integration of high-Q inductors and transformers places the magnetic field direction parallel to the substrate plane without requiring high aspect ratio processing. The photolithographically patterned coil structure includes an elastic member having an intrinsic stress profile. The intrinsic stress profile biases a free portion away from the substrate forming a loop winding. An anchor portion remains fixed to the substrate. The free portion end becomes a second anchor portion which may be connected to the substrate via soldering or plating. A series of individual coil structures can be joined via their anchor portions to form inductors and transformers.
    Type: Application
    Filed: May 23, 2002
    Publication date: February 6, 2003
    Applicant: Xerox Corporation
    Inventors: Christopher L. Chua, Francesco Lemmi, Koenraad F. Van Schuylenbergh, Jeng Ping Lu, David K. Fork, Eric Peeters, Decai Sun, Donald L. Smith, Linda T. Romano
  • Publication number: 20020110757
    Abstract: Several methods and structures for improving the yield of out-of-plane micro-device structures including springs and coils are described. In one method the springs used to form out-of-plane structures are constrained via a tether to avoid bunching and entanglement. The high yield structure may be used in numerous electronic applications such as filter circuits.
    Type: Application
    Filed: February 9, 2001
    Publication date: August 15, 2002
    Applicant: Xerox Corporation
    Inventors: David K. Fork, Ping Mei, Koenraad F. Van Schuylenbergh
  • Publication number: 20020110761
    Abstract: Several methods and structures for improving the yield of out-of-plane micro-device structures including springs and coils are described. In one method the elastic members have graded perforations for controlling rate of release. In another method and structure, a layout enables the contact landing area to be increased. The high yield structures may be used in numerous electronic applications such as filter circuits.
    Type: Application
    Filed: February 9, 2001
    Publication date: August 15, 2002
    Applicant: Xerox Corporation
    Inventors: David K. Fork, Christopher L. Chua, Koenraad F. Van Schuylenbergh, Noble M. Johnson, David K. Biegelsen
  • Patent number: 6396677
    Abstract: A new type of high-Q variable capacitor includes a substrate, a first electrically conductive layer fixed to the substrate, a dielectric layer fixed to a portion of the electrically conductive layer, and a second electrically conductive layer having an anchor portion and a free portion. The anchor portion is fixed to the dielectric layer and the free portion is initially fixed to the dielectric layer, but is released from the dielectric layer to become separated from the dielectric layer, and wherein an inherent stress profile in the second electrically conductive layer biases the free portion away from the dielectric layer. When a bias voltage is applied between the first electrically conductive layer and the second electrically conductive layer, electrostatic forces in the free portion bend the free portion towards the first electrically conductive layer, thereby increasing the capacitance of the capacitor.
    Type: Grant
    Filed: May 17, 2000
    Date of Patent: May 28, 2002
    Assignee: Xerox Corporation
    Inventors: Christopher L. Chua, Eric Peeters, Koenraad F. Van Schuylenbergh, Donald L. Smith