Abstract: An encoding system which prevents deterioration of a picture quality and provides a high encoding efficiency even when the size of a block is increased to enhance an encoding efficiency. An input image which is divided into blocks by a blocking unit, is supplied to a plurality of encoders which perform encoding in different numbers of tone levels respectively. Respective pieces of encoded image information from the respective encoders are supplied in common to a selector. A block classification unit determines the degree of the tone gradient of an input block and then outputs the classification result to the selector. The selector, in accordance with the block classification result, selects one of the respective pieces of the encoded image information and outputs the selected one as selected encoded image information. For example, when the tone varies greatly, there is selected the encoder which has a small number of tone levels and a high resolution.

Abstract: An image coding device including a dividing circuit for dividing an input image signal into a plurality of image areas, a coding method deciding circuit for deciding a coding method for a target one of the image areas, a binary image coder for coding a binary image in the target image area to obtain a binary image code, a nonbinary image coder for coding a nonbinary image in the target image area to obtain a nonbinary image code, a character/background separating circuit for separating a character/background synthesized image in the target image area into a character portion and a background portion and supplying the character portion and the background portion to the binary image coder and the nonbinary image coder, respectively, and a control circuit for selectively operating the binary image coder and the nonbinary image coder according to a decision result from the coding method deciding circuit.

Abstract: An image coding apparatus includes a color component. converter 2 for converting an input image signal 1 into predetermined color spaces which have been subdivided into independent color components, a segmenting circuit 4 for subdividing the converted image signals into predetermined image regions for the respective color components, a color information selecting circuit 9 for judging a condition of the color component of the input image based upon the components of the input image for each image region, and also a coding device 5 for performing a coding process with respect to the respective color components. In the color information selecting circuit 9, a judgement is made whether or not there is color information by comparing the pixel component of the pixel within the input image block with a predetermined threshold value. When it is judged that the input image block corresponds to the monochromatic information, the color difference component is not transferred or not stored.

Abstract: A vector quantizer which transmits the input vector of the time when the minimum distortion is larger than the preset distortion threshold value and stores such input vector into the second code book as the new quantizing representative vector for the use in the successive vector quantizing processes.Further, since the first and second code book constitute in the form of tree-structure, calculation for search may be executed at a high speed.

Abstract: A digital signal processor of a simple circuit configuration capable of implementing arithmetic processes and interruption processes efficiently in a reduced number of steps at a high processing speed. The digital signal processor comprises instruction execution pipeline stages including a stage in which data is read from a data memory and the data is applied to an arithmetic unit; an arithmetic unit for the execution stage, including a barrel shifter, a multiplier and an arithmetic and logic unit, a normalizing barrel shifter, a round-off/accumulation adder, internal data memories and a DMA transfer bus for a write/accumulation stage, an address generating unit capable of parallel and two-dimensional generation of two inputs one output data memory addresses and a DMA control unit for controlling the two-dimensional data transfer through a DMA bus between the internal data memories and an external data memory for an instruction execution stage.

Abstract: A digital signal processor of a simple circuit configuration capable of implementing arithmetic processes and interruption processes efficiently in a reduced number of steps at a high processing speed. The digital signal processor comprises instruction execution pipeline stages including a stage in which data is read from a data memory and the data is applied to an arithmetic unit; an arithmetic unit for the execution stage, including a barrel shifter, a multiplier and an arithmetic and logic unit, a normalizing barrel shifter, a round-off/accumulation adder, internal data memories and a DMA transfer bus for a write/accumulation stage, an address generating unit capable of parallel and two-dimensional generation of two inputs one output data memory addresses and a DMA control unit for controlling the two-dimensional data transfer through a DMA bus between the internal data memories and an external data memory for an instruction execution stage.

Abstract: A digital signal processor of a simple circuit configuration capable of implementing arithmetic processes and interruption processes efficiently in a reduced number of steps at a high processing speed. The digital signal processor comprises instruction execution pipeline stages including a stage in which data is read from a data memory and the data is applied to an arithmetic unit; an arithmetic unit for the execution stage, including a barrel shifter, a multiplier and an arithmetic and logic unit, a normalizing barrel shifter, a round-off/accumulation adder, internal data memories and a DMA transfer bus for a write/accumulation stage, an address generating unit capable of parallel and two-dimensional generation of two inputs one output data memory addresses and a DMA control unit for controlling the two-dimensional data transfer through a DMA bus between the internal data memories and an external data memory for an instruction execution stage.

Abstract: A digital signal processor of a simple circuit configuration capable of implementing arithmetic processes and interruption processes efficiently in a reduced number of steps at a high processing speed. The digital signal processor comprises instruction execution pipeline stages including a stage in which data is read from a data memory and the data is applied to an arithmetic unit; an arithmetic unit for the execution stage, including a barrel shifter, a multiplier and an arithmetic and logic unit, a normalizing barrel shifter, a round-off/accumulation adder, internal data memories and a DMA transfer bus for a write/accumulation stage, an address generating unit capable of parallel and two-dimensional generation of two inputs one output data memory addresses and a DMA control unit for controlling the two-dimensional data transfer through a DMA bus between the internal data memories and an external data memory for an instruction execution stage.

Abstract: A vector quantizer which transmits the input vector of the time when the minimum distortion is larger than the preset distortion threshold value and stores such input vector into the second code book as the new quantizing representative vector for the use in the successive vector quantizing processes. Further, since the first and second code book constitute in the form of tree-structure, calculation for search may be executed at a high speed.

Abstract: The present invention improves a digital signal processor, more particularly, calculation methods for motion compensation in reducing a required amount of calculations when an amount of distortion between a last frame block and a current frame block; in processing a direct memory access at a higher efficiency; in processing a subdivided data calculation at a higher speed; in processing a branch instruction occurring in the pipeline process at a higher efficiency; and in processing an interruption occurring in a repeat process operation at greater convenience, and furthermore in reducing a required amount of calculations through minimum distortion searching processes hierarchized.

Abstract: A digital signal processing apparatus which is used for the computation of coding image signals or the like and a motion compensative operation method which uses a digital signal processing apparatus. The apparatus comprises a plurality of signal processing means arranged in parallel and control means which assigns loads to the signal processing means so that the signal processing means have even computation volumes. Alternatively, an address generator is provided for each of data sets entered independently. An intermediate check is conducted during the computation for a block which involves a motion compensative operation.

Abstract: A video codec system inputs consecutively frame after frame of sub-sampled video data obtained by sub-sampling video data in units of frames. The video data is coded in parallel by internal coding circuits. This averages the numbers of significant pixels in the sub-sampled video data to be processed. The coded video data is composed so as to comply with specifications of the receiving equipment. Upon transmission, the data is again sub-sampled depending on the number of coding circuits on the receiving side. Each piece of the sub-sampled data is given a header for consecutive transmission. This allows for a certain period of time between pieces of data that arrive at the receiving side, thereby eliminating time differences in receiving and coding.

Abstract: A digital signal processor of a simple circuit configuration capable of implementing arithmetic processes and interruption processes efficiently in a reduced number of steps at a high processing speed. The digital signal processor comprises instruction execution pipeline stages including a stage in which data is read from a data memory and the data is applied to an arithmetic unit; an arithmetic unit for the execution stage, including a barrel shifter, a multiplier and an arithmetic and logic unit, a normalizing barrel shifter, a round-off/accumulation adder, internal data memories and a DMA transfer bus for a write/accumulation stage, an address generating unit capable of parallel and two-dimensional generation of two inputs one output data memory addresses and a DMA control unit for controlling the two-dimensional data transfer through a DMA bus between the internal data memories and an external data memory for an instruction execution stage.

Abstract: An interframe video data coding and decoding apparatus utilizes a differential amplitude suppression circuit in combination with a block encoder and a motion detector to non-linearly suppress amplitude values of interframe differential block data based on a motion detection threshold value determined by an encoding control circuit. The determined threshold value is based on the amount of encoded data being stored in a transmission buffer memory. The suppressed amplitude differential block data is added to corresponding blocks in a frame memory to update the contents of the frame memory during each frame of input video data. In another embodiment, vector quantization encoders are utilized to transmit a motion vector index with encoded frame differential data.

Abstract: A digital signal processor comprises a bus structure including a program bus, data bus and data input/output bus, a program memory, a program controller, an internal data memory made up of a plurality of 2-port memories for storing block data, an arithmetic operator, a DMA controller for implementing block data input/output between the internal data memory and an external data memory in parallel to an internal operation by the arithmetic operator, an address generator for generating addresses for the internal operation and DMA transfer concurrently and in parallel to the internal operation, and parallel data input/output ports for implementing parallel data communication with an external device independently of input/output operations and in asynchronous fashion. The processor executes an intricate adaptive process algorism such as image signal processing at high speed and at high throughput.

Abstract: A substrate multimedia data transmission control system in which transmission frame bits set in a unit of a transmission frame having a repeating cycle of 8 KHz according to the present invention enables it to effect a realtime multiplexed bit allocation in the 8 kbps unit in a variable fashion such that an automatic matching of a transmission frame is achieved at an initiation of a transmission and error check bits of the error correction code are contained in a transmission frame with a satisfactory matching. In addition, the multiframe configuration according to the present invention enables it to handle in an integrated fashion the synchronizations of the voice data frame, the error correction frame, and the video data packet, which as a result minimizes the size of the buffer memories disposed to send and/or to receive motion video and which enables the transmission speed smoothing operation to be accomplished in a simple configuration through an easy control.

Abstract: In an interframe adaptive quantization encoding apparatus to perform efficient encoding of video signals using vector quantization method, analog signals raster-scanned from the left to the right on the screen and from the upper side to the lower side are converted into digital signals, the digital signals per every m picture elements x n lines are made a block and the block data is subjected to mean value separation in a vector quantization encoder thereby input vector is formed, inner product between the input vector and output vector read from a code book ROM is estimated by an inner product operation circuit, and maximum value of the inner product is estimated by a maximum inner product detection circuit and made amplitude coefficient, thereby efficient encoding is performed.

Abstract: A digital signal processor comprises a bus structure including a program bus, data bus and data input/output bus, a program memory, a program controller, an internal data memory made up of a plurality of 2-port memories for storing block data, an arithmetic operator, a DMA controller for implementing block data input/output between the internal data memory and an external data memory in parallel to an internal operation by the arithmetic operator, an address generator for generating addresses for the internal operation and DMA transfer concurrently and in parallel to the internal operation, and parallel data input/output ports for implementing parallel data communication with an external device independently of input/output operations and in asynchronous fashion. The processor executes an intricate adaptive process algorism such as image signal processing at high speed and at high throughput.