Patents by Inventor Koh Yoshikawa

Koh Yoshikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240088214
    Abstract: An edge termination structure portion has one or more guard rings of a second conductivity type that are provided between a well region and an end side of a semiconductor substrate, and are exposed to an upper surface of the semiconductor substrate, a first conductivity type region that is provided between a first guard ring that is closest to the well region, among the one or more guard rings, and the well region, and a first field plate that is provided above the upper surface of the semiconductor substrate, and is connected to the first guard ring, and the first field plate overlaps 90% or more of the first conductivity type region between the first guard ring and the well region.
    Type: Application
    Filed: November 20, 2023
    Publication date: March 14, 2024
    Inventor: Koh YOSHIKAWA
  • Publication number: 20230369137
    Abstract: A semiconductor device includes trench portions arrayed in a first direction on an upper surface side of a semiconductor substrate, a first conductivity type lower surface region provided in a part of a lower surface of the semiconductor substrate, a second conductivity type base region provided on the upper surface side, a first conductivity type first region disposed between the base region and the lower surface region, a first conductivity type upper surface region provided on an upper surface of the semiconductor substrate, and a second conductivity type bottom region disposed continuously in the first direction to be in contact with bottom portions of the trench portions. In a cross section along the first direction and perpendicular to the upper and lower surfaces and passing through the lower surface region, one end portion of the bottom region in the first direction locates directly above the lower surface region.
    Type: Application
    Filed: July 14, 2023
    Publication date: November 16, 2023
    Inventors: Motoyoshi KUBOUCHI, Kosuke YOSHIDA, Soichi YOSHIDA, Koh YOSHIKAWA, Nao SUGANUMA
  • Publication number: 20230282737
    Abstract: Provided is a semiconductor device including: a semiconductor substrate; gate trench portions; an emitter electrode; a mesa portion; an emitter region of a first conductivity type provided on an upper surface of the mesa portion and in contact with the gate trench portions; a contact region of a second conductivity type provided on the upper surface of the mesa portion; a base region of a second conductivity type provided below the emitter region and the contact region, in contact with the gate trench portions, and having a lower doping concentration than the contact region; a drift region of a first conductivity type provided below the base region and having a lower doping concentration than the emitter region; and a high resistance portion provided between the emitter electrode and the base region in a depth direction of the semiconductor substrate and having a higher resistance than the emitter region.
    Type: Application
    Filed: January 23, 2023
    Publication date: September 7, 2023
    Inventor: Koh YOSHIKAWA
  • Patent number: 11749675
    Abstract: Between a source electrode (25) of a main device (24) and a current sensing electrode (22) of a current detection device (21), a resistor for detecting current is connected. Dielectric withstand voltage of gate insulator (36) is larger than a product of the resistor and maximal current flowing through the current detection device (21) with reverse bias. A diffusion length of a p-body region (32) of the main device (24) is shorter than that of a p-body (31) of the current detection device (21). A curvature radius at an end portion of the p-body region (32) of the main device (24) is smaller than that of the p-body (31) of the current detection device (21). As a result, at the inverse bias, electric field at the end portion of the p-body region (32) of the main device (24) becomes stronger than that of the p-body region (31) of the current detection device (21). Consequently, avalanche breakdown tends to occur earlier in the main device 24 than the current detection device (21).
    Type: Grant
    Filed: January 7, 2021
    Date of Patent: September 5, 2023
    Assignees: FUJI ELECTRIC CO., LTD., DENSO CORPORATION
    Inventors: Seiji Momota, Hitoshi Abe, Takashi Shiigi, Takeshi Fujii, Koh Yoshikawa, Tetsutaro Imagawa, Masaki Koyama, Makoto Asai
  • Patent number: 11742249
    Abstract: A fabrication method for a semiconductor device includes measuring a thickness of a semiconductor substrate in which a bulk donor of a first conductivity type is entirely distributed, adjusting an implantation condition in accordance with the thickness of the semiconductor substrate and implanting hydrogen ions from a lower surface of the semiconductor substrate to an upper surface side of the semiconductor substrate, and annealing the semiconductor substrate and forming, in a passage region through which the hydrogen ions have passed, a first high concentration region of the first conductivity type in which a donor concentration is higher than a doping concentration of the bulk donor.
    Type: Grant
    Filed: September 5, 2022
    Date of Patent: August 29, 2023
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Motoyoshi Kubouchi, Kosuke Yoshida, Soichi Yoshida, Koh Yoshikawa, Nao Suganuma
  • Publication number: 20230085529
    Abstract: Provided is a semiconductor device including: a semiconductor substrate having a drift region of a first conductivity type; an active portion, in which at least one of a transistor portion and a diode portion is provided, in the semiconductor substrate; and an edge termination structure portion provided farther outward than the active portion in the semiconductor substrate, wherein the edge termination structure portion has a plurality of guard rings of a second conductivity type provided in contact with an upper surface of the semiconductor substrate, and an embedded dielectric film arranged between two guard rings and at least partially embedded in the semiconductor substrate, and the guard rings are provided up to a position below the embedded dielectric film.
    Type: Application
    Filed: August 22, 2022
    Publication date: March 16, 2023
    Inventors: Kosuke YOSHIDA, Koh Yoshikawa, Nao Suganuma
  • Publication number: 20230081512
    Abstract: Provided is a semiconductor device including a semiconductor substrate having a first dopant of a first conductivity type and a second dopant of a second conductivity type, both the first dopant and the second dopant being distributed in an entire part of the semiconductor substrate, the semiconductor substrate including a drift region of the first conductivity type, a dielectric film provided on an upper surface of the semiconductor substrate, a high concentration region of the first conductivity type provided in contact with the dielectric film below the dielectric film and having a higher doping concentration than the drift region, and a fall off region that is provided in contact with the dielectric film below the dielectric film and in which a concentration of the dopant of the second conductivity type decreases toward the dielectric film.
    Type: Application
    Filed: August 22, 2022
    Publication date: March 16, 2023
    Inventors: Koh YOSHIKAWA, Kosuke YOSHIDA, Nao SUGANUMA
  • Publication number: 20230040096
    Abstract: A fabrication method for a semiconductor device includes measuring a thickness of a semiconductor substrate in which a bulk donor of a first conductivity type is entirely distributed, adjusting an implantation condition in accordance with the thickness of the semiconductor substrate and implanting hydrogen ions from a lower surface of the semiconductor substrate to an upper surface side of the semiconductor substrate, and annealing the semiconductor substrate and forming, in a passage region through which the hydrogen ions have passed, a first high concentration region of the first conductivity type in which a donor concentration is higher than a doping concentration of the bulk donor.
    Type: Application
    Filed: September 5, 2022
    Publication date: February 9, 2023
    Inventors: Motoyoshi KUBOUCHI, Kosuke YOSHIDA, Soichi YOSHIDA, Koh YOSHIKAWA, Nao SUGANUMA
  • Patent number: 11450734
    Abstract: A semiconductor device includes an edge terminal structure portion provided between the active portion and an end portion of the semiconductor substrate on an upper surface of the semiconductor substrate, in which the edge terminal structure portion has a first high concentration region of the first conductivity type which has a donor concentration higher than a doping concentration of the bulk donor in a region between the upper surface and a lower surface of the semiconductor substrate, an upper surface of the first high concentration region is located on an upper surface side of the semiconductor substrate, and a lower surface of the first high concentration region is located on a lower surface side of the semiconductor substrate.
    Type: Grant
    Filed: June 11, 2020
    Date of Patent: September 20, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Motoyoshi Kubouchi, Kosuke Yoshida, Soichi Yoshida, Koh Yoshikawa, Nao Suganuma
  • Patent number: 11245010
    Abstract: A semiconductor device having a semiconductor substrate that includes a first-conductivity-type substrate and a first-conductivity-type epitaxial layer, and a plurality of trenches reaching a predetermined depth from a main surface of the semiconductor substrate to terminate in the first-conductivity-type epitaxial layer. The semiconductor substrate includes a hydrogen-donor introduced part, of which a concentration of a hydrogen donor is greatest at a depth position that is separate from bottoms of the trenches by a distance at least two times of the depth of the trenches. The impurity concentration of an impurity dopant of the first-conductivity-type substrate being lower than that of the first-conductivity-type epitaxial layer.
    Type: Grant
    Filed: September 3, 2020
    Date of Patent: February 8, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Kosuke Yoshida, Haruo Nakazawa, Kenichi Iguchi, Koh Yoshikawa, Motoyoshi Kubouchi
  • Publication number: 20210384330
    Abstract: Provided is a semiconductor device, including: a semiconductor substrate including a bulk donor; an active portion provided on the semiconductor substrate; and an edge termination structure portion provided between the active portion and an end side of the semiconductor substrate on a upper surface of the semiconductor substrate; wherein the active portion includes hydrogen, and has a first high concentration region with a higher donor concentration than a bulk donor concentration; and the edge termination structure portion, which is provided in a range that is wider than the first high concentration region in a depth direction of the semiconductor substrate, includes hydrogen, and has a second high concentration region with a higher donor concentration than the bulk donor concentration.
    Type: Application
    Filed: August 24, 2021
    Publication date: December 9, 2021
    Inventors: Koh YOSHIKAWA, Masayuki MOMOSE, Toshiyuki MATSUI
  • Publication number: 20210134789
    Abstract: Between a source electrode (25) of a main device (24) and a current sensing electrode (22) of a current detection device (21), a resistor for detecting current is connected. Dielectric withstand voltage of gate insulator (36) is larger than a product of the resistor and maximal current flowing through the current detection device (21) with reverse bias. A diffusion length of a p-body region (32) of the main device (24) is shorter than that of a p-body (31) of the current detection device (21). A curvature radius at an end portion of the p-body region (32) of the main device (24) is smaller than that of the p-body (31) of the current detection device (21). As a result, at the inverse bias, electric field at the end portion of the p-body region (32) of the main device (24) becomes stronger than that of the p-body region (31) of the current detection device (21). Consequently, avalanche breakdown tends to occur earlier in the main device 24 than the current detection device (21).
    Type: Application
    Filed: January 7, 2021
    Publication date: May 6, 2021
    Applicants: FUJI ELECTRIC CO., LTD., DENSO CORPORATION
    Inventors: Seiji Momota, Hitoshi Abe, Takashi Shiigi, Takeshi Fujii, Koh Yoshikawa, Tetsutaro Imagawa, Masaki Koyama, Makoto Asai
  • Publication number: 20210111248
    Abstract: A semiconductor device having a semiconductor substrate that includes a first-conductivity-type substrate and a first-conductivity-type epitaxial layer, and a plurality of trenches reaching a predetermined depth from a main surface of the semiconductor substrate to terminate in the first-conductivity-type epitaxial layer. The semiconductor substrate includes a hydrogen-donor introduced part, of which a concentration of a hydrogen donor is greatest at a depth position that is separate from bottoms of the trenches by a distance at least two times of the depth of the trenches. The impurity concentration of an impurity dopant of the first-conductivity-type substrate being lower than that of the first-conductivity-type epitaxial layer.
    Type: Application
    Filed: September 3, 2020
    Publication date: April 15, 2021
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Kosuke YOSHIDA, Haruo NAKAZAWA, Kenichi IGUCHI, Koh YOSHIKAWA, Motoyoshi KUBOUCHI
  • Patent number: 10916541
    Abstract: Between a source electrode (25) of a main device (24) and a current sensing electrode (22) of a current detection device (21), a resistor for detecting current is connected. Dielectric withstand voltage of gate insulator (36) is larger than a product of the resistor and maximal current flowing through the current detection device (21) with reverse bias. A diffusion length of a p-body region (32) of the main device (24) is shorter than that of a p-body (31) of the current detection device (21). A curvature radius at an end portion of the p-body region (32) of the main device (24) is smaller than that of the p-body (31) of the current detection device (21). As a result, at the inverse bias, electric field at the end portion of the p-body region (32) of the main device (24) becomes stronger than that of the p-body region (31) of the current detection device (21). Consequently, avalanche breakdown tends to occur earlier in the main device 24 than the current detection device (21).
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: February 9, 2021
    Assignees: FUJI ELECTRIC CO., LTD., DENSO CORPORATION
    Inventors: Seiji Momota, Hitoshi Abe, Takashi Shiigi, Takeshi Fujii, Koh Yoshikawa, Tetsutaro Imagawa, Masaki Koyama, Makoto Asai
  • Publication number: 20200395215
    Abstract: A semiconductor device includes an edge terminal structure portion provided between the active portion and an end portion of the semiconductor substrate on an upper surface of the semiconductor substrate, in which the edge terminal structure portion has a first high concentration region of the first conductivity type which has a donor concentration higher than a doping concentration of the bulk donor in a region between the upper surface and a lower surface of the semiconductor substrate, an upper surface of the first high concentration region is located on an upper surface side of the semiconductor substrate, and a lower surface of the first high concentration region is located on a lower surface side of the semiconductor substrate.
    Type: Application
    Filed: June 11, 2020
    Publication date: December 17, 2020
    Inventors: Motoyoshi KUBOUCHI, Kosuke YOSHIDA, Soichi YOSHIDA, Koh YOSHIKAWA, Nao SUGANUMA
  • Patent number: 10109501
    Abstract: A semiconductor device having a voltage resistant structure in a first aspect of the present invention is provided, comprising a semiconductor substrate, a semiconductor layer on the semiconductor substrate, a front surface electrode above the semiconductor layer, a rear surface electrode below the semiconductor substrate, an extension section provided to a side surface of the semiconductor substrate, and a resistance section electrically connected to the front surface electrode and the rear surface electrode. The extension section may have a lower permittivity than the semiconductor substrate. The resistance section may be provided to at least one of the upper surface and the side surface of the extension section.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: October 23, 2018
    Assignees: FUJI ELECTRIC CO., LTD., Octec, Inc.
    Inventors: Koh Yoshikawa, Haruo Nakazawa, Kenichi Iguchi, Yasukazu Seki, Katsuya Okumura
  • Publication number: 20180006125
    Abstract: A semiconductor device having a voltage resistant structure in a first aspect of the present invention is provided, comprising a semiconductor substrate, a semiconductor layer on the semiconductor substrate, a front surface electrode above the semiconductor layer, a rear surface electrode below the semiconductor substrate, an extension section provided to a side surface of the semiconductor substrate, and a resistance section electrically connected to the front surface electrode and the rear surface electrode. The extension section may have a lower permittivity than the semiconductor substrate. The resistance section may be provided to at least one of the upper surface and the side surface of the extension section.
    Type: Application
    Filed: September 1, 2017
    Publication date: January 4, 2018
    Inventors: Koh YOSHIKAWA, Haruo NAKAZAWA, Kenichi IGUCHI, Yasukazu SEKI, Katsuya OKUMURA
  • Patent number: 9825145
    Abstract: When p-type impurities are implanted into a SiC substrate using a laser, controlling the concentration is difficult. A p-type impurity region is formed by a laser in a region where the control of the concentration in the SiC substrate is not necessary almost at all. A SiC semiconductor device having withstanding high voltage is manufactured at a lower temperature process compared to ion implantation process. A method of manufacturing a silicon carbide semiconductor device includes forming, on one main surface of a first conductivity-type silicon carbide substrate, a first conductivity-type drift layer having a lower concentration than that of the silicon carbide substrate; forming, on a front surface side of the drift layer, a second conductivity-type electric field control region by a laser doping technology; forming a Schottky electrode in contact with the drift layer; and forming, on the other main surface of the silicon carbide substrate, a cathode electrode.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: November 21, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Koh Yoshikawa, Haruo Nakazawa, Kenichi Iguchi, Yasukazu Seki
  • Patent number: 9786749
    Abstract: A semiconductor device having a voltage resistant structure in a first aspect of the present invention is provided, comprising a semiconductor substrate, a semiconductor layer on the semiconductor substrate, a front surface electrode above the semiconductor layer, a rear surface electrode below the semiconductor substrate, an extension section provided to a side surface of the semiconductor substrate, and a resistance section electrically connected to the front surface electrode and the rear surface electrode. The extension section may have a lower permittivity than the semiconductor substrate. The resistance section may be provided to at least one of the upper surface and the side surface of the extension section.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: October 10, 2017
    Assignees: FUJI ELECTRIC CO., LTD., Octec, Inc.
    Inventors: Koh Yoshikawa, Haruo Nakazawa, Kenichi Iguchi, Yasukazu Seki, Katsuya Okumura
  • Publication number: 20170148882
    Abstract: A semiconductor device having a voltage resistant structure in a first aspect of the present invention is provided, comprising a semiconductor substrate, a semiconductor layer on the semiconductor substrate, a front surface electrode above the semiconductor layer, a rear surface electrode below the semiconductor substrate, an extension section provided to a side surface of the semiconductor substrate, and a resistance section electrically connected to the front surface electrode and the rear surface electrode. The extension section may have a lower permittivity than the semiconductor substrate. The resistance section may be provided to at least one of the upper surface and the side surface of the extension section.
    Type: Application
    Filed: September 29, 2016
    Publication date: May 25, 2017
    Inventors: Koh YOSHIKAWA, Haruo NAKAZAWA, Kenichi IGUCHI, Yasukazu SEKI, Katsuya OKUMURA