Abstract: A circuit device is configured to switching between a first mode in which phase noise of an output clock signal is lower than that in a second mode and the second mode in which power consumption is smaller than that in the first mode, and the circuit device includes an oscillation circuit configured to generate an oscillation signal, a waveform shaping circuit configured to perform waveform shaping on the oscillation signal to obtain a rectangular wave clock signal; and an output circuit configured to output the output clock signal based on the clock signal. A driving capability of the waveform shaping circuit in the first mode is higher than a driving capability of the waveform shaping circuit in the second mode.

Abstract: A circuit device is configured to switching between a first mode in which phase noise of an output clock signal is lower than that in a second mode and the second mode in which power consumption is smaller than that in the first mode, and the circuit device includes an oscillation circuit configured to generate an oscillation signal, a waveform shaping circuit configured to perform waveform shaping on the oscillation signal to obtain a rectangular wave clock signal; and an output circuit configured to output the output clock signal based on the clock signal. A driving capability of the waveform shaping circuit in the first mode is higher than a driving capability of the waveform shaping circuit in the second mode.

Abstract: A circuit device includes a waveform-shaping circuit that waveform-shapes an oscillation signal and provides an output clock signal based on a clock signal. A bias voltage output circuit of the circuit device provides a bias voltage of the oscillation signal that is input to the waveform-shaping circuit. A comparator of the circuit device compares a DC voltage obtained by smoothing the clock signal with a reference voltage. A logic circuit of the circuit device sets an adjustment value of the bias voltage. In a test mode of the logic circuit, the logic circuit changes the adjustment value to determine a set value of the adjustment value based on output of the comparator when the adjustment value is changed and stores the determined set value in a storage circuit.

Abstract: A circuit apparatus includes an oscillation circuit that generates an oscillation signal, a first buffer circuit that outputs a first clock signal based on the oscillation signal, a second buffer circuit that outputs a second clock signal based on the first clock signal, a first terminal electrically couplable to a first node via which the first buffer circuit outputs the first clock signal, and a second terminal electrically coupled to a second node via which the second buffer circuit outputs the second clock signal, and the rise period of the first clock signal is shorter than the rise period of the second clock signal.

Abstract: A circuit device includes: an output circuit including a waveform-shaping circuit of an oscillation signal and configured to output an output clock signal based on a clock signal subjected to waveform-shaping; a bias voltage output circuit configured to output a bias voltage of the oscillation signal input to the waveform-shaping circuit; a comparator configured to compare a DC voltage obtained by smoothing the clock signal subjected to the waveform-shaping with a reference voltage; a logic circuit configured to set an adjustment value of the bias voltage; and a storage circuit. In a test mode, the logic circuit changes the adjustment value to determine a set value of the adjustment value based on output of the comparator when the adjustment value is changed, and stores the determined set value in the storage circuit.

Abstract: The circuit device includes a first MOS transistor of a first conductivity type a source of which is coupled to a first power supply voltage node, a second MOS transistor of a second conductivity type a source of which is coupled to a second power supply voltage node, a first variable resistance circuit which is coupled between a drain of the first MOS transistor and an output node, and which includes a first switch, and a second switch coupled between the drain of the first MOS transistor and the second power supply voltage node. The control circuit performs control of making the first switch OFF and making the second switch ON when the clock signal fails to be output from the output node, and making the first switch ON and making the second switch OFF when the clock signal is output from the output node.

Abstract: A circuit apparatus includes an oscillation circuit that generates an oscillation signal, a first buffer circuit that outputs a first clock signal based on the oscillation signal, a second buffer circuit that outputs a second clock signal based on the first clock signal, a first terminal electrically couplable to a first node via which the first buffer circuit outputs the first clock signal, and a second terminal electrically coupled to a second node via which the second buffer circuit outputs the second clock signal, and the rise period of the first clock signal is shorter than the rise period of the second clock signal.

Abstract: The circuit device includes a first MOS transistor of a first conductivity type a source of which is coupled to a first power supply voltage node, a second MOS transistor of a second conductivity type a source of which is coupled to a second power supply voltage node, a first variable resistance circuit which is coupled between a drain of the first MOS transistor and an output node, and which includes a first switch, and a second switch coupled between the drain of the first MOS transistor and the second power supply voltage node. The control circuit performs control of making the first switch OFF and making the second switch ON when the clock signal fails to be output from the output node, and making the first switch ON and making the second switch OFF when the clock signal is output from the output node.