Patents by Inventor Kohei Eguchi

Kohei Eguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8256035
    Abstract: A toilet seat handle including a substantially L-shaped handle main body formed with a handle member and a base member having a receiving section, an elongated hook element slidably provided inside the base member of the handle main body and formed at its tip end with a claw, and an adjustment screw screw-engaged with the base end of the hook element. The toilet seat handle is mounted on a toilet seat by sandwiching a part of the seat with the claw of the hook element and the receiving section of the base member with the tightened adjustment screw.
    Type: Grant
    Filed: August 19, 2011
    Date of Patent: September 4, 2012
    Inventor: Kohei Eguchi
  • Patent number: 7881609
    Abstract: A ranging signal R1 generated by a signal generator and reaches to a signal checker via a working system transmission line, a loop circuit, and an auxiliary system transmission line. The signal checker measures a delay time from the generation to the arrival of the signal R1. A ranging signal R2 generated by the signal generator and reaches to a signal checker via an auxiliary system transmission line, a loop circuit, and an auxiliary system transmission line. The signal checker measures a delay time from the generation to the arrival of the signal R12. A delay time of the working system transmission line is calculated from the delay times of the signals R1 and R2. Disruption of the services provided by the other ONUs can be prevented since the working system transmission line is not used for upstream communication of the ranging signals R1 and R2.
    Type: Grant
    Filed: December 20, 2007
    Date of Patent: February 1, 2011
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Kohei Eguchi
  • Publication number: 20080267624
    Abstract: A ranging signal R1 generated by a signal generator and reaches to a signal checker via a working system transmission line, a loop circuit, and an auxiliary system transmission line. The signal checker measures a delay time from the generation to the arrival of the signal R1. A ranging signal R2 generated by the signal generator and reaches to a signal checker via an auxiliary system transmission line, a loop circuit, and an auxiliary system transmission line. The signal checker measures a delay time from the generation to the arrival of the signal R12. A delay time of the working system transmission line is calculated from the delay times of the signals R1 and R2. Disruption of the services provided by the other ONUs can be prevented since the working system transmission line is not used for upstream communication of the ranging signals R1 and R2.
    Type: Application
    Filed: December 20, 2007
    Publication date: October 30, 2008
    Applicant: OKI ELECTRIC INDUSTRY CO., LTD.
    Inventor: Kohei Eguchi
  • Publication number: 20080260385
    Abstract: A signal processing apparatus for use in an optical line termination or optical network unit in a gigabit passive optical network encapsulates Ethernet signals, time-division multiplexed signals, and asynchronous transfer mode signals in the same way in a novel type of frame. The same input and output circuits can accordingly be used to support all three types of communication. A low-cost chip set including at least the input and output circuits of the apparatus can be combined with conversion circuits as necessary to provide a flexible answer to the needs of specific gigabit passive optical network systems.
    Type: Application
    Filed: November 5, 2007
    Publication date: October 23, 2008
    Applicant: OKI ELECTRIC INDUSTRY CO., LTD.
    Inventor: Kohei Eguchi
  • Publication number: 20050242377
    Abstract: A semiconductor device and a method for manufacturing the same and method for deleting information in use of the semiconductor device, in which field shield isolation or a trench type isolation between elements is used with suppression of penetration of field oxide into element active region of the device, that is, a defect involved in conventional LOGOS type process, are disclosed. A non-LOCOS insulating device isolation block is formed in a semiconductor substrate. The non-LOCOS insulating device isolation block uses a field shield element isolation structure or trench type element isolation structure.
    Type: Application
    Filed: June 30, 2005
    Publication date: November 3, 2005
    Applicant: UNITED MICROELECTRONICS CORPORATION
    Inventors: Kohei Eguchi, Yuichi Egawa, Shoichi Iwasa, Hideki Fujikake, Wataru Yokozeki, Tatsuya Kawamata
  • Patent number: 6917076
    Abstract: A semiconductor device and a method for manufacturing the same and method for deleting information in use of the semiconductor device, in which field shield isolation or a trench type isolation between elements is used with suppression of penetration of field oxide into element active region of the device, that is, a defect involved in conventional LOCOS type process, are disclosed. A non-LOCOS insulating device isolation block is formed in a semiconductor substrate. The non-LOCOS insulating device isolation block uses a field shield element isolation structure or trench type element isolation structure.
    Type: Grant
    Filed: July 31, 2003
    Date of Patent: July 12, 2005
    Assignee: United Microelectronics Corporation
    Inventors: Kohei Eguchi, Yuichi Egawa, Shoichi Iwasa, Hideki Fujikake, Wataru Yokozeki, Tatsuya Kawamata
  • Publication number: 20040021160
    Abstract: A semiconductor device and a method for manufacturing the same and method for deleting information in use of the semiconductor device, in which field shield isolation or a trench type isolation between elements is used with suppression of penetration of field oxide into element active region of the device, that is, a defect involved in conventional LOCOS type process, are disclosed. A non-LOCOS insulating device isolation block is formed in a semiconductor substrate. The non-LOCOS insulating device isolation block uses a field shield element isolation structure or trench type element isolation structure.
    Type: Application
    Filed: July 31, 2003
    Publication date: February 5, 2004
    Inventors: Kohei Eguchi, Yuichi Egawa, Shoichi Iwasa, Hideki Fujikake, Wataru Yokozeki, Tatsuya Kawamata
  • Patent number: 6657229
    Abstract: A semiconductor device has field shield isolation or trench type isolation between elements which suppresses penetration of field oxide into an element active region of the device. A common gate is located between two MOS transistors, which may be of opposite conductivity type. After gate electrode wiring layers are formed in a field region and an active region to the same level, a pad polysilicon film formed on the entire surface to cover the patterns of these gate electrode wiring layers, which are in separated patterns.
    Type: Grant
    Filed: August 24, 1999
    Date of Patent: December 2, 2003
    Assignee: United Microelectronics Corporation
    Inventors: Kohei Eguchi, Yuichi Egawa, Shoichi Iwasa, Hideki Fujikake, Wataru Yokozeki, Tatsuya Kawamata
  • Patent number: 6656781
    Abstract: A semiconductor device has, in one embodiment, two wells of different conductivity types formed in a semiconductor substrate. The two wells are arranged to be adjacent to each other to form a junction therebetween. A field oxide film is formed to cover the junction at a main surface of the semiconductor substrate. Other field oxide films or field-shield isolation structures may be formed to isolate circuit elements from one another in the wells.
    Type: Grant
    Filed: October 3, 2002
    Date of Patent: December 2, 2003
    Assignee: Nippon Steel Corporation
    Inventors: Atsushi Kawasaki, Kohei Eguchi, Katsuki Hazama, Fumitaka Sugaya
  • Patent number: 6526053
    Abstract: A packet transmitting method of processing a packet having a control information area and a user information area by a functional block in a node and, thereafter, transmitting the packet from the node. Whether information of the user information area is useless for the user or not is discriminated on the basis of information of the control information area or the user information area. The packet judged to be useless is converted into a predetermined format in which the number of alternating times of a bit pattern has been reduced and the packet is allowed to pass through the functional block. The bit pattern of the packet is returned to a state before the conversion at least before the packet is transmitted from the node.
    Type: Grant
    Filed: March 15, 1999
    Date of Patent: February 25, 2003
    Assignee: Oki Electric Industry Co, Ltd.
    Inventors: Kazuo Ishiba, Kohei Eguchi
  • Publication number: 20030027384
    Abstract: A semiconductor device has, in one embodiment, two wells of different conductivity types formed in a semiconductor substrate. The two wells are arranged to be adjacent to each other to form a junction therebetween. A field oxide film is formed to cover the junction at a main surface of the semiconductor substrate. Other field oxide films or field-shield isolation structures may be formed to isolate circuit elements from one another in the wells.
    Type: Application
    Filed: October 3, 2002
    Publication date: February 6, 2003
    Inventors: Atsushi Kawasaki, Kohei Eguchi, Katsuki Hazama, Fumitaka Sugaya
  • Patent number: 6486013
    Abstract: A semiconductor device has, in one embodiment, two wells of different conductivity types formed in a semiconductor substrate. The two wells are arranged to be adjacent to each other to form a junction therebetween. A field oxide film is formed to cover the junction at a main surface of the semiconductor substrate. Other field oxide films or field-shield isolation structures may be formed to isolate circuit elements from one another in the wells.
    Type: Grant
    Filed: January 8, 2001
    Date of Patent: November 26, 2002
    Assignee: Nippon Steel Corporation
    Inventors: Atsushi Kawasaki, Kohei Eguchi, Katsuki Hazama, Fumitaka Sugaya
  • Patent number: 6482692
    Abstract: A semiconductor device has, in one embodiment, two wells of different conductivity types formed in a semiconductor substrate. The two wells are arranged to be adjacent to each other to form a junction therebetween. A field oxide film is formed to cover the junction at a main surface of the semiconductor substrate. Other field oxide films or field-shield isolation structures may be formed to isolate circuit elements from one another in the wells.
    Type: Grant
    Filed: November 30, 2000
    Date of Patent: November 19, 2002
    Assignee: Nippon Steel Corporation
    Inventors: Atsushi Kawasaki, Kohei Eguchi, Katsuki Hazama, Fumitaka Sugaya
  • Publication number: 20010000922
    Abstract: A semiconductor device has, in one embodiment, two wells of different conductivity types formed in a semiconductor substrate. The two wells are arranged to be adjacent to each other to form a junction therebetween. A field oxide film is formed to cover the junction at a main surface of the semiconductor substrate. Other field oxide films or field-shield isolation structures may be formed to isolate circuit elements from one another in the wells.
    Type: Application
    Filed: January 8, 2001
    Publication date: May 10, 2001
    Inventors: Atsushi Kawasaki, Kohei Eguchi, Katsuki Hazama, Fumitaka Sugaya
  • Publication number: 20010000412
    Abstract: A semiconductor device has, in one embodiment, two wells of different conductivity types formed in a semiconductor substrate. The two wells are arranged to be adjacent to each other to form a junction therebetween. A field oxide film is formed to cover the junction at a main surface of the semiconductor substrate. Other field oxide films or field-shield isolation structures may be formed to isolate circuit elements from one another in the wells.
    Type: Application
    Filed: November 30, 2000
    Publication date: April 26, 2001
    Inventors: Atsushi Kawasaki, Kohei Eguchi, Katsuki Hazama, Fumitaka Sugaya
  • Patent number: 6201275
    Abstract: A semiconductor device has, in one embodiment, two wells of different conductivity types formed in a semiconductor substrate. The two wells are arranged to be adjacent to each other to form a junction therebetween. A field oxide film is formed to cover the junction at a main surface of the semiconductor substrate. Other field oxide films or field-shield isolation structures may be formed to isolate circuit elements from one another in the wells.
    Type: Grant
    Filed: June 24, 1996
    Date of Patent: March 13, 2001
    Assignee: Nippon Steel Corporation
    Inventors: Atsushi Kawasaki, Kohei Eguchi, Katsuki Hazama, Fumitaka Sugaya
  • Patent number: 6093575
    Abstract: When a capacitor is formed on a semiconductor substrate, a lower electrode of the capacitor is first formed. After an insulating film is formed on the lower electrode, it is selectively etched until the lower electrode is exposed, and in this way, a hole portion is formed in the insulating film. After a ferroelectric film is formed inside the hole portion and on the insulating film, the ferroelectric film is polished and removed by a chemical-mechanical polishing method in such a manner as to leave the ferroelectric film inside the hole portion. Thereafter, an upper electrode of the capacitor is formed on the ferroelectric film.
    Type: Grant
    Filed: April 9, 1998
    Date of Patent: July 25, 2000
    Assignee: Nippon Steel Corporation
    Inventor: Kohei Eguchi
  • Patent number: 5714787
    Abstract: In a semiconductor device and a method for manufacturing the semiconductor device, a width of an element isolation region is reduced by a field-shield. A silicon oxide film of a side wall of a polycrystal silicon film is fabricated by thermally oxidizing a side wall of the polycrystal silicon film, while using a silicon nitride film as an antioxidation film. A width of a field-shield electrode made of the polycrystal silicon film is made smaller than a limit value of the very fine processing.
    Type: Grant
    Filed: December 5, 1995
    Date of Patent: February 3, 1998
    Assignee: Nippon Steel Corporation
    Inventors: Kohei Eguchi, Akio Ishikawa