Abstract: A data transmission circuit analyzes video data and a pixel clock input from a video/audio signal processor, and determines whether the signals are valid or not. If a signal is invalid, the data transmission circuit generates and outputs a TMDS signal based on dummy video data and a dummy pixel clock internally generated as pseudo signals. Accordingly, a state in which an invalid signal is being output can be prevented, and the time required to output video can be reduced because an additional device authentication is not performed.

Abstract: A format converter resolution converts first video data input to a video input device, thereby generating second video data. An HDMI converter converts the second video data into an HDMI signal. A first clock generator generates a second clock signal having a frequency corresponding to a resolution of the second video data based on a first clock signal input to the video input device and supplies the second clock signal to the format converter and the HDMI converter. A second clock generator generates a third clock signal having a frequency corresponding to a resolution of the HDMI signal and supplies the third clock signal to the HDMI converter. The format converter converts the first video data into the second video data based on the first clock signal and the second clock signal. The HDMI converter converts the second video data into the HDMI signal based on the second clock signal and the third clock signal.

Abstract: When an unreceivable audio sampling frequency is transmitted from an audio data transmitting device or received at an audio data receiving device, frequency changing processing is executed inside an HDMI LSI of the transmitter side or the receiver side to change the unreceivable audio sampling frequency to a frequency that can be received at the audio data receiving device based on EDID information retained in the audio data receiving device, and mute processing of the audio information is executed to prevent generation of strange sounds.