Abstract: A layout pattern of a demultiplexer circuit of a display device employing the SSD method is configured as described below. Specifically, demultiplexers in the demultiplexer circuit are grouped with three demultiplexers as one set, and nine transistors as switching elements included in the three demultiplexers of each set are arranged to be aligned in the extending direction of a source line with three transistors as a unit while positions of the nine transistors are sequentially shifted in the vertical direction with respect to the source line. Furthermore, any two adjacent sets are arranged such that a direction in which nine transistors included in one set are shifted in the vertical direction with three transistors as a unit and a direction in which nine transistors in the other set are shifted in the above-described vertical direction with three transistors as a unit are opposite to each other.

Abstract: A layout pattern of a demultiplexer circuit of a display device employing the SSD method is configured as described below. Specifically, demultiplexers in the demultiplexer circuit are grouped with three demultiplexers as one set, and nine transistors as switching elements included in the three demultiplexers of each set are arranged to be aligned in the extending direction of a source line with three transistors as a unit while positions of the nine transistors are sequentially shifted in the vertical direction with respect to the source line. Furthermore, any two adjacent sets are arranged such that a direction in which nine transistors included in one set are shifted in the vertical direction with three transistors as a unit and a direction in which nine transistors in the other set are shifted in the above-described vertical direction with three transistors as a unit are opposite to each other.

Abstract: A layout pattern of a demultiplexer circuit of a display device employing the SSD method is configured as described below. Specifically, demultiplexers in the demultiplexer circuit are grouped with three demultiplexers as one set, and nine transistors as switching elements included in the three demultiplexers of each set are arranged to be aligned in the extending direction of a source line with three transistors as a unit while positions of the nine transistors are sequentially shifted in the vertical direction with respect to the source line. Furthermore, any two adjacent sets are arranged such that a direction in which nine transistors included in one set are shifted in the vertical direction with three transistors as a unit and a direction in which nine transistors in the other set are shifted in the above-described vertical direction with three transistors as a unit are opposite to each other.

Abstract: A layout pattern of a demultiplexer circuit of a display device employing the SSD method is configured as described below. Specifically, demultiplexers in the demultiplexer circuit are grouped with three demultiplexers as one set, and nine transistors as switching elements included in the three demultiplexers of each set are arranged to be aligned in the extending direction of a source line with three transistors as a unit while positions of the nine transistors are sequentially shifted in the vertical direction with respect to the source line. Furthermore, any two adjacent sets are arranged such that a direction in which nine transistors included in one set are shifted in the vertical direction with three transistors as a unit and a direction in which nine transistors in the other set are shifted in the above-described vertical direction with three transistors as a unit are opposite to each other.

Abstract: An active matrix substrate includes pixel lines disposed in a display area and connected to pixels, respectively, a signal input section for inputting a signal to the pixel lines, and connection lines connected to the signal input section and the pixel lines. The pixel lines include a short pixel line having a smaller line length than other pixel lines. The connection lines include a short pixel connection line connected to the short pixel line and other connection lines connected to the other pixel lines, one connection line of the short pixel connection line and the other connection lines includes a line resistance adjusting section that adjusts a line resistance of the one connection line according to an electric resistance of the pixel line connected to the one connection line.

Abstract: An active matrix substrate includes pixel lines disposed in a display area and connected to pixels, respectively, a signal input section for inputting a signal to the pixel lines, and connection lines connected to the signal input section and the pixel lines. The pixel lines include a short pixel line having a smaller line length than other pixel lines. The connection lines include a short pixel connection line connected to the short pixel line and other connection lines connected to the other pixel lines, one connection line of the short pixel connection line and the other connection lines includes a line resistance adjusting section that adjusts a line resistance of the one connection line according to an electric resistance of the pixel line connected to the one connection line.

Abstract: On a panel substrate, there are a wide region where the wiring pitch between gate bus lines is relatively wide and a narrow region where the wiring pitch between the gate bus lines is relatively narrow. A shift register operates based on a gate start pulse signal and gate clock signals whose pulse widths are set to N (N is an integer not less than two) times a length of one horizontal scan period. A generation period of a pulse of a gate clock signal that brings one gate bus line constituting a gate bus line pair (two adjacent gate bus lines) into a selected state and a generation period of a pulse of a gate clock signal that brings the other gate bus line constituting the gate bus line pair into the selected state overlap for at least one horizontal scanning period.

Abstract: A display device includes: an mth scanning signal line to which a plurality of sub pixels are connected; an nth scanning signal line to which a sub pixel is connected, the number of sub pixels which are connected to the nth scanning signal line being lower than the number of sub pixels which are connected to the mth scanning signal line; and a driver circuit which includes a plurality of output circuits and which drives the mth scanning signal line and the nth scanning signal line, an mth one of the plurality of output circuits including an mth output transistor connected to the mth scanning signal line, an nth one of the plurality of output circuits including an nth output transistor connected to the nth scanning signal line, a driving capability of the nth output transistor being lower than that of the mth output transistor.

Abstract: Luminance unevenness in a display area having an irregular shape is suppressed. An edge of the display area includes an irregularly-shaped edge which is curved. An end part of a signal switching circuit is located on an outer side of the irregularly-shaped edge. A driver is provided so as not to overlap with the end part of the signal switching circuit, as viewed in a first direction. An nth scanning signal line crosses the irregularly-shaped edge, passes through a space between the irregularly-shaped edge and the end part of the signal switching circuit, and is drawn to the driver, as viewed from above.

Abstract: The present invention reliably and sufficiently corrects a voltage variation in data signal lines in a display device resulting when sampling analog video signals, while suppressing increase in layout area. In a data signal line drive circuit of an active matrix liquid crystal display device, a video signal Svi is sampled by an Nch transistor (SWk) which has a parasitic capacitance (Cgd) that causes a voltage drop in a data signal line SL3(i?1)+k (i=1 through n; k=1, 2, 3). To correct this, an inversion delayer (342) makes logical inversion of the transistor (SWk)'s control signal Sck and delays the inverted signal for a predetermined time to generate an inversion delayed signal Srdk, and applies this inversion delayed signal Srd to the data signal line 3(i?1)+k via a correction capacitance element (Cc). The inversion delayer (342) makes the inversion delayed signal Srdk start its change from an L level voltage to a H level voltage after the Nch transistor (SWk) has assumed an OFF state.

Abstract: The present invention reliably and sufficiently corrects a voltage variation in data signal lines in a display device resulting when sampling analog video signals, while suppressing increase in layout area. In a data signal line drive circuit of an active matrix liquid crystal display device, a video signal Svi is sampled by an Nch transistor (SWk) which has a parasitic capacitance (Cgd) that causes a voltage drop in a data signal line SL3(i?1)+k (i=1 through n; k=1, 2, 3). To correct this, an inversion delayer (342) makes logical inversion of the transistor (SWk)'s control signal Sck and delays the inverted signal for a predetermined time to generate an inversion delayed signal Srdk, and applies this inversion delayed signal Srd to the data signal line 3(i?1)+k via a correction capacitance element (Cc). The inversion delayer (342) makes the inversion delayed signal Srdk start its change from an L level voltage to a H level voltage after the Nch transistor (SWk) has assumed an OFF state.