Patents by Inventor Kohei KAWABATA

Kohei KAWABATA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240094756
    Abstract: Provided is a semiconductor device with a reference voltage circuit including an enhancement type transistor having P-type polycrystalline silicon as a first gate electrode, and a depletion type transistor having N-type polycrystalline silicon as a second gate electrode, in which the enhancement type transistor has an impermeable film that is locally provided to cover the first gate electrode via an interlayer insulating film disposed on the first gate electrode, and a nitride film that has an opening portion which is provided larger than the first gate electrode and smaller than the impermeable film, and is provided to cover a periphery of the impermeable film, and the depletion type transistor has a nitride film that is directly provided on an interlayer insulating film disposed on the second gate electrode and covers the depletion type transistor without a gap.
    Type: Application
    Filed: November 10, 2023
    Publication date: March 21, 2024
    Applicant: ABLIC INC.
    Inventors: Takeshi KOYAMA, Hisashi Hasegawa, Shinjiro Kato, Kohei Kawabata
  • Patent number: 11587869
    Abstract: A semiconductor device includes a semiconductor substrate, a field-effect transistor arranged at least partially on the semiconductor substrate and used in an analog circuit, and having a P-type gate electrode, an interlayer insulating film arranged on the field-effect transistor, and a hydrogen shielding metal or metallic film arranged on the interlayer insulting film and covering the P-type gate electrode and configured to shield hydrogen.
    Type: Grant
    Filed: October 28, 2020
    Date of Patent: February 21, 2023
    Assignee: ABLIC INC.
    Inventors: Hisashi Hasegawa, Takeshi Koyama, Shinjiro Kato, Kohei Kawabata
  • Publication number: 20220137658
    Abstract: Provided is a semiconductor device with a reference voltage circuit including an enhancement type transistor having P-type polycrystalline silicon as a first gate electrode, and a depletion type transistor having N-type polycrystalline silicon as a second gate electrode, in which the enhancement type transistor has an impermeable film that is locally provided to cover the first gate electrode via an interlayer insulating film disposed on the first gate electrode, and a nitride film that has an opening portion which is provided larger than the first gate electrode and smaller than the impermeable film, and is provided to cover a periphery of the impermeable film, and the depletion type transistor has a nitride film that is directly provided on an interlayer insulating film disposed on the second gate electrode and covers the depletion type transistor without a gap.
    Type: Application
    Filed: October 27, 2021
    Publication date: May 5, 2022
    Inventors: Takeshi KOYAMA, Hisashi HASEGAWA, Shinjiro KATO, Kohei KAWABATA
  • Publication number: 20210134714
    Abstract: A semiconductor device includes a semiconductor substrate, a field-effect transistor arranged on the semiconductor substrate and used in an analog circuit, and having a P-type gate electrode, an interlayer insulating film arranged on the field-effect transistor, and a hydrogen shielding metal film arranged on the interlayer insulting film and covering the P-type gate electrode and configured to shield hydrogen.
    Type: Application
    Filed: October 28, 2020
    Publication date: May 6, 2021
    Inventors: Hisashi HASEGAWA, Takeshi KOYAMA, Shinjiro KATO, Kohei KAWABATA
  • Publication number: 20190318997
    Abstract: Provided is a semiconductor device capable of shielding X-rays irradiated from a side surface side of a semiconductor substrate and a method of manufacturing the same. The semiconductor device includes: gate insulating film; a gate electrode; a source/drain region; an element isolation region; a guard ring surrounding the element isolation region; an interlayer insulating film; a contact trench in the interlayer insulating film; a barrier metal film for shielding X-rays covering inner side surfaces and a bottom surface of the contact trench; and a metal film connected to the guard ring.
    Type: Application
    Filed: April 8, 2019
    Publication date: October 17, 2019
    Inventors: Kohei KAWABATA, Masahiro HATAKENAKA