Patents by Inventor Kohei Miyagawa

Kohei Miyagawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8269274
    Abstract: In a semiconductor substrate of a first conductivity type, first to third drain offset regions of a second conductivity type are formed in that order in a bottom up manner. A body region of the first conductivity type is formed partly in the second drain offset region and partly in the third drain offset region. The second drain offset region has a lower impurity concentration than the first and third drain offset regions. A curvature portion of the body region is located in the second drain offset region.
    Type: Grant
    Filed: November 5, 2009
    Date of Patent: September 18, 2012
    Assignee: Panasonic Corporation
    Inventors: Kohei Miyagawa, Yasushi Kobayashi, Daigo Yamashina
  • Patent number: 7880141
    Abstract: In the resin film evaluation method and method for manufacturing a semiconductor device applying the resin film evaluation method of the present invention, first, a substrate having a resin film formed on an insulating film with an opening in which the surface of the insulating film is exposed is irradiated with charged energetic particles. Then, the surface potentials of the substrate surface irradiated with charged energetic particles are measured. Based on the measurements, the difference in surface potential between the resin film and the insulating film exposed in the opening is obtained. Based on the difference in surface potential, a physical quantity such as the resin film residue count obtained after a given treatment is predicted. In this way, the degenerated layer formed on the surface of a resin film due to charged energetic particles such as implantation ions can be evaluated in a simple and highly accurate manner.
    Type: Grant
    Filed: November 28, 2007
    Date of Patent: February 1, 2011
    Assignee: Panasonic Corporation
    Inventors: Hisako Kamiyanagi, Satoshi Sibata, Reiki Kaneki, Kohei Miyagawa
  • Publication number: 20100187606
    Abstract: A manufacturing method of a semiconductor device including an LDMOS transistor includes: a process (a) of forming a first conductive well diffusion layer in the semiconductor substrate; a process (b) of sequentially forming a gate insulator film, a gate conductive film, and a photoresist film on a region on the semiconductor substrate corresponding to the well diffusion layer; a process (c) of performing photolithography to remove a part of the photoresist film formed in a predetermined region, and etching the gate conductive film using a remaining part of the photoresist film as a mask so as to form an opening in the predetermined region; a process (d) of doping second conductive impurity ions using a remaining part of the gate conductive film and the remaining part of the photoresist film as a mask so as to form the body layer; and a process (e) of removing the remaining part of the gate conductive film except a part corresponding to the gate electrode formed based on a part that constitutes a lateral surfa
    Type: Application
    Filed: January 20, 2010
    Publication date: July 29, 2010
    Inventors: Yasushi KOBAYASHI, Masaki Inoue, Kohei Miyagawa
  • Publication number: 20100123194
    Abstract: In a semiconductor substrate of a first conductivity type, first to third drain offset regions of a second conductivity type are formed in that order in a bottom up manner. A body region of the first conductivity type is formed partly in the second drain offset region and partly in the third drain offset region. The second drain offset region has a lower impurity concentration than the first and third drain offset regions. A curvature portion of the body region is located in the second drain offset region.
    Type: Application
    Filed: November 5, 2009
    Publication date: May 20, 2010
    Inventors: Kohei MIYAGAWA, Yasushi Kobayashi, Daigo Yamashina
  • Publication number: 20080128616
    Abstract: In the resin film evaluation method and method for manufacturing a semiconductor device applying the resin film evaluation method of the present invention, first, a substrate having a resin film formed on an insulating film with an opening in which the surface of the insulating film is exposed is irradiated with charged energetic particles. Then, the surface potentials of the substrate surface irradiated with charged energetic particles are measured. Based on the measurements, the difference in surface potential between the resin film and the insulating film exposed in the opening is obtained. Based on the difference in surface potential, a physical quantity such as the resin film residue count obtained after a given treatment is predicted. In this way, the degenerated layer formed on the surface of a resin film due to charged energetic particles such as implantation ions can be evaluated in a simple and highly accurate manner.
    Type: Application
    Filed: November 28, 2007
    Publication date: June 5, 2008
    Inventors: Hisako Kamiyanagi, Satoshi Sibata, Reiki Kaneki, Kohei Miyagawa