Abstract: This semiconductor device comprises a peripheral region surrounding a cell region, a gate electrode disposed in the peripheral region, and an emitter electrode. The emitter electrode includes a cell electrode portion, a peripheral electrode portion formed at a distance from the cell electrode portion in the peripheral region, and a connecting portion connecting the cell electrode portion and the peripheral electrode portion. The peripheral region includes a well region formed to surround the cell region, an insulating film and an intermediate insulating film that cover the well region, and a gate finger embedded in the insulating films. The connecting portion is formed across the gate finger on the intermediate insulating film. The peripheral electrode portion is electrically connected to the well region.

Abstract: This semiconductor device includes: an n-type drift layer; a p-type base region; a trench extending in the depth direction so as to pass through the base region and reach the drift layer; an insulating film formed on an inner surface of the trench; a gate trench surrounding the insulating film; and a p-type column region provided on the drift layer at a position at the bottom of the trench. The drift layer includes: a first region having a first concentration peak; and a second region that is provided at a position deeper than the trench and corresponding to the column region, and has a second concentration peak lower than the first concentration peak.

Abstract: A semiconductor device includes a semiconductor layer, a first conductive type first region formed in a surface layer portion of a first principal surface of the semiconductor layer, a cell structure having a second conductive type second region formed in a surface layer portion of the first region, a first conductive type third region formed in the surface layer portion of the first region such that third region is in contact with the second region, and a control electrode opposing the second region via a first insulating film adjacent to the second region, the control electrode forming a current path in the second region, a first electrode layer formed on the first principal surface such that the first electrode layer covers the cell structure, and electrically connected to the third region, a second electrode layer formed on the first principal surface separately from the first electrode layer.

Abstract: A semiconductor device includes a semiconductor layer which has a first principal surface and a second principal surface, a first conductive type drift region which is formed inside the semiconductor layer, a second conductive type base region which is formed on a surface layer portion of the drift region, a plurality of trench structures which include a first trench structure, a second trench structure and a third trench structure that are formed at intervals on the first principal surface so as to penetrate through the base region, a first region which is partitioned between the first trench structure and the second trench structure in the semiconductor layer, a second region which is partitioned between the second trench structure and the third trench structure in the semiconductor layer, a channel region which is controlled by the first trench structure, and a first conductive type high concentration region.

Abstract: A semiconductor device includes: a semiconductor layer of a first conductivity type having a first main surface and a second main surface; an active region defined in a surface layer of the first main surface; an outer region defined outside the active region in the surface layer; and a main junction region of a second conductivity type provided in the outer region as surrounding the active region. The semiconductor device includes: a floating region of the second conductivity type provided in an electrically floating state in the active region; a region isolation trench structure which isolates the floating region in the surface layer; an outer isolation trench structure disposed in spaced relation from the region isolation trench structure to define the main junction region outward thereof; and an intervening region disposed between the region isolation trench structure and the outer isolation trench structure.

Abstract: A semiconductor device includes a semiconductor layer that has a main surface and that includes an active region, a first-conductivity-type first impurity region formed at a surface layer portion of the main surface of the semiconductor layer, a second-conductivity-type field limit region formed along a peripheral edge of the active region in a surface layer portion of the first impurity region, and a second-conductivity-type low concentration region that has a second-conductivity-type impurity concentration lower than a second-conductivity-type impurity concentration of the field limit region and that is formed along a peripheral edge of the field limit region in a region on a side opposite to the active region with respect to the field limit region in the surface layer portion of the first impurity region.

Abstract: A semiconductor device includes a semiconductor layer that has a main surface and that includes an active region, a first-conductivity-type first impurity region formed at a surface layer portion of the main surface of the semiconductor layer, a second-conductivity-type field limit region formed along a peripheral edge of the active region in a surface layer portion of the first impurity region, and a second-conductivity-type low concentration region that has a second-conductivity-type impurity concentration lower than a second-conductivity-type impurity concentration of the field limit region and that is formed along a peripheral edge of the field limit region in a region on a side opposite to the active region with respect to the field limit region in the surface layer portion of the first impurity region.