Abstract: A device includes a semiconductor substrate including a first well region and a second well region; a first transistor including a first gate insulating layer provided above the first well region, a first gate electrode having a semiconductor, and a second gate electrode having a metal; a second transistor including a second gate insulating layer provided above the second well region, a third gate electrode having a semiconductor, and a fourth gate electrode having a metal; an element isolation area disposed between the first and second well regions; and a first insulating layer formed above the element isolation area. The first insulating layer has a first portion extending over the first gate electrode and a second portion extending over the third gate electrode, a portion of the second gate electrode is formed above the first portion, and a portion of the fourth gate electrode is formed above the second portion.

Abstract: According to one embodiment, a semiconductor device includes a first region including a memory cell and a second region including a peripheral circuit. The second region includes a diffusion region provided on a surface of the semiconductor layer, a gate insulating film provided on the diffusion region, a gate electrode provided on the gate insulating film, an insulator layer provided on the diffusion region and surrounding the gate electrode, and an element isolation that is embedded in the semiconductor layer and surrounds the diffusion region. The element isolation includes a first region that is recessed below the surface of the diffusion region and a second region that is between the diffusion region and the first region and includes a protrusion protruding to a level higher than the first region.

Abstract: According to one embodiment, a semiconductor memory device includes a substrate, a first semiconductor region, a second semiconductor region, an insulating layer, a gate electrode film, a gate insulating film, a first film, a second film, a first contact plug, and a second contact plug. The second film and the first film are arranged in the first direction. The first contact plug extends in the first film along a second direction. The second direction crosses the first direction. The first contact plug electrically connects to the first semiconductor region. The second contact plug extends in the second film along the second direction. The second contact plug electrically connects to the second semiconductor region. At least a part of the gate electrode film dose not overlap the first film in the second direction and dose not overlap the second film in the second direction.

Abstract: A semiconductor memory device according to one embodiment includes a substrate, a first stacked body provided on the substrate, a second stacked body provided on the first stacked body, a first semiconductor pillar extending in the first stacked body and the second stacked body, a first memory film provided between the first semiconductor pillar and the first electrode films, a first interconnect, a second interconnect, a first plug and a second plug. The first stacked body includes a plurality of first electrode films and a plurality of first insulating films. The second stacked body includes a plurality of second electrode films and a plurality of second insulating films. The first plug electrically connects the plurality of second electrode films to each other. The second plug electrically connects the plurality of second electrode films to each other.