Patents by Inventor Kohei SAKO

Kohei SAKO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240113208
    Abstract: A semiconductor device according to an aspect of the present disclosure, includes a semiconductor layer in which a trench is formed, a buried electrode provided inside the trench, an upper electrode provided above the buried electrode inside the trench, an insulating film provided inside the trench, a first electrode provided on an upper surface of the semiconductor layer, and a second electrode provided on a lower surface of the semiconductor layer, wherein the insulating film includes a first portion between the buried electrode and a side wall of the trench, a second portion between the upper electrode and the side wall of the trench, and a third portion between the buried electrode and the upper electrode, and a lower surface of the upper electrode has a dent in a central portion.
    Type: Application
    Filed: March 8, 2023
    Publication date: April 4, 2024
    Applicant: Mitsubishi Electric Corporation
    Inventors: Kohei SAKO, Yuji EBIIKE, Kazuya INOUE
  • Patent number: 11495663
    Abstract: A predetermined relational expression holds where a first distance along the in-plane direction from a channel of the first semiconductor layer to a third semiconductor layer that is the other of the collector layer and the cathode layer is designated as W, a second distance from the channel of the first semiconductor layer to the second semiconductor layer is designated as S, and a diffusion coefficient and a lifetime of a part of the semiconductor substrate between the channel of the first semiconductor layer and the third semiconductor layer are designated as D and ?, respectively.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: November 8, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kakeru Otsuka, Hirofumi Oki, Kohei Sako
  • Patent number: 11456376
    Abstract: A semiconductor device includes an IGBT region and a diode region provided to be adjacent to each other in a semiconductor substrate further includes: a boundary trench having, in a position in which the IGBT region and the diode region are adjacent to each other in plan view, a bottom surface positioned in a drift layer to be deeper than an active trench or a dummy trench, and one side wall and another side wall that face each other; and a boundary trench gate electrode, which faces a base layer, an anode layer, and the drift layer via a boundary trench insulating film and is provided from the one side wall to the other side wall of the boundary trench across a region that faces the drift layer in the boundary trench.
    Type: Grant
    Filed: March 17, 2021
    Date of Patent: September 27, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kohei Sako, Tetsuo Takahashi, Hidenori Fujii
  • Publication number: 20220013636
    Abstract: A predetermined relational expression holds where a first distance along the in-plane direction from a channel of the first semiconductor layer to a third semiconductor layer that is the other of the collector layer and the cathode layer is designated as W, a second distance from the channel of the first semiconductor layer to the second semiconductor layer is designated as S, and a diffusion coefficient and a lifetime of a part of the semiconductor substrate between the channel of the first semiconductor layer and the third semiconductor layer are designated as D and ?, respectively.
    Type: Application
    Filed: March 15, 2021
    Publication date: January 13, 2022
    Applicant: Mitsubishi Electric Corporation
    Inventors: Kakeru OTSUKA, Hirofumi OKI, Kohei SAKO
  • Publication number: 20210384335
    Abstract: A semiconductor device includes an IGBT region and a diode region provided to be adjacent to each other in a semiconductor substrate further includes: a boundary trench having, in a position in which the IGBT region and the diode region are adjacent to each other in plan view, a bottom surface positioned in a drift layer to be deeper than an active trench or a dummy trench, and one side wall and another side wall that face each other; and a boundary trench gate electrode, which faces a base layer, an anode layer, and the drift layer via a boundary trench insulating film and is provided from the one side wall to the other side wall of the boundary trench across a region that faces the drift layer in the boundary trench.
    Type: Application
    Filed: March 17, 2021
    Publication date: December 9, 2021
    Applicant: Mitsubishi Electric Corporation
    Inventors: Kohei SAKO, Tetsuo TAKAHASHI, Hidenori FUJII