Patents by Inventor Kohei Tatsumi

Kohei Tatsumi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240165921
    Abstract: Provided is a joining structure in which two joined bodies composed of metal are firmly joined together with plated metal, and a method for manufacturing the joining structure. The joining structure comprises a first joined body composed of a first metal, a second joined body composed of a second metal, and a plating portion, disposed between the first joined body and the second joined body, formed of a plating metal, and joining the first joined body and the second joined body. In the plating portion a joining interface of plating metal is formed at around equidistance from the respective joined surfaces of the first joined body and the second joined body, and the plating portion comprises, in the vicinity of the joining interface, has a recrystallization region where the plating metal has recrystallized, or a first diffusion region where the plating metal has diffused.
    Type: Application
    Filed: February 28, 2022
    Publication date: May 23, 2024
    Inventor: Kohei TATSUMI
  • Publication number: 20240128391
    Abstract: Provide is a solar cell module includes: a solar cell; an electrode provided on a surface of the solar cell; a wiring material formed of metal; and plating portions formed of a plating metal between the electrode and the wiring material to join the solar cell and the wiring material. The electrode is a bus bar electrode extending from a first edge of the solar cell to a second edge opposing the first edge, the wiring material is in the form of a strip or wire and is arranged to extend in the direction of the bus bar electrode, and the plating portions are formed at predetermined intervals in the extension direction of the wiring material and locally join the bus bar electrode and the wiring material.
    Type: Application
    Filed: February 28, 2022
    Publication date: April 18, 2024
    Inventor: Kohei TATSUMI
  • Patent number: 11810885
    Abstract: A semiconductor element bonding structure capable of strongly bonding a semiconductor element and an object to be bonded and relaxing thermal stress caused by a difference in thermal expansion, by interposing metal particles and Ni between the semiconductor element and the object to be bonded, the metal particles having a lower hardness than Ni and having a micro-sized particle diameter. A plurality of metal particles 5 (aluminum (Al), for example) having a lower hardness than nickel (Ni) and having a micro-sized particle diameter are interposed between a semiconductor chip 3 and a substrate 2 to be bonded to the semiconductor chip 3, and the metal particles 5 are fixedly bonded by the nickel (Ni). Optionally, aluminum (Al) or an aluminum alloy (Al alloy) is used as the metal particles 5, and aluminum (Al) or an aluminum alloy (Al alloy) is used on the surface of the semiconductor chip 3 and/or the surface of the substrate 2.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: November 7, 2023
    Assignee: WASEDA UNIVERSITY
    Inventors: Kohei Tatsumi, Yasunori Tanaka
  • Patent number: 11152286
    Abstract: A power semiconductor module device includes: a plurality of semiconductor elements that are arranged at intervals and flush with each other on a plane; an insulating support that fixes the semiconductor elements; a first thick-film plating layer that is formed as a first-surface-side electrode that electrically connects the semiconductor elements to each other on at least one surface of a front surface side and a rear surface side. The first thick-film plating layer supports the semiconductor elements from at least one of an upper direction and a lower direction.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: October 19, 2021
    Assignee: WASEDA UNIVERSITY
    Inventor: Kohei Tatsumi
  • Publication number: 20210225794
    Abstract: A semiconductor element bonding structure capable of strongly bonding a semiconductor element and an object to be bonded and relaxing thermal stress caused by a difference in thermal expansion, by interposing metal particles and Ni between the semiconductor element and the object to be bonded, the metal particles having a lower hardness than Ni and having a micro-sized particle diameter. A plurality of metal particles 5 (aluminum (Al), for example) having a lower hardness than nickel (Ni) and having a micro-sized particle diameter are interposed between a semiconductor chip 3 and a substrate 2 to be bonded to the semiconductor chip 3, and the metal particles 5 are fixedly bonded by the nickel (Ni). Optionally, aluminum (Al) or an aluminum alloy (Al alloy) is used as the metal particles 5, and aluminum (Al) or an aluminum alloy (Al alloy) is used on the surface of the semiconductor chip 3 and/or the surface of the substrate 2.
    Type: Application
    Filed: February 26, 2021
    Publication date: July 22, 2021
    Inventors: Kohei Tatsumi, Yasunori Tanaka
  • Patent number: 10903146
    Abstract: [Problem] To provide an electrode connection structure and the like in which a plurality of elongated leads are arranged in parallel and a longitudinal side surface of each lead is connected to an electrode by plating treatment with high quality. [Solution] An electrode connection structure in which a semiconductor chip 12 electrode and/or a substrate electrode is connected to a plurality of elongated leads 11 of a lead frame 10 by plating. The plurality of elongated leads 11 of the lead frame 10 are arranged in parallel, and a longitudinal side surface of each lead 11 is connected to the semiconductor chip 12 electrode and/or the substrate electrode by plating.
    Type: Grant
    Filed: March 7, 2017
    Date of Patent: January 26, 2021
    Assignees: WASEDA UNIVERSITY, MITSUI HIGH-TEC, INC.
    Inventors: Kohei Tatsumi, Kazutoshi Ueda, Nobuaki Sato, Koji Shimizu
  • Publication number: 20190229103
    Abstract: A semiconductor device includes: a first switching element that is provided on a high side; a first diode element that is connected in parallel to the first switching element; a second switching element that is provide on a low side and connected in series to the first switching element; and a second diode element that is connected in parallel to the second switching element, wherein the first switching element and one of the first diode element and the second diode element are stacked adjacently to each other in a vertical direction of respective electrode surfaces thereof via a conductive electrode, the second switching element and the other of the first diode element and the second diode element that is different from the diode element adjacent to the first switching element are stacked adjacently to each other in a vertical direction of respective electrode surfaces thereof via a conductive electrode, and the first switching element and the second switching element are not adjacent in a vertical direction
    Type: Application
    Filed: January 25, 2019
    Publication date: July 25, 2019
    Applicants: WASEDA UNIVERSITY, MITSUI HIGH-TEC., INC., TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Kohei TATSUMI, Kazuhito KAMEI, Rikiya Kamimura, Koji SHIMIZU, Kazutoshi UEDA, Nobuaki SATO, Keiji TODA, Masayuki HIKITA, Akihiro IMAKIIRE
  • Publication number: 20190198428
    Abstract: A power semiconductor module device includes: a plurality of semiconductor elements that are arranged at intervals and flush with each other on a plane; an insulating support that fixes the semiconductor elements; a first thick-film plating layer that is formed as a first-surface-side electrode that electrically connects the semiconductor elements to each other on at least one surface of a front surface side and a rear surface side. The first thick-film plating layer supports the semiconductor elements from at least one of an upper direction and a lower direction.
    Type: Application
    Filed: January 22, 2019
    Publication date: June 27, 2019
    Inventor: Kohei Tatsumi
  • Publication number: 20190103341
    Abstract: [Problem] To provide an electrode connection structure and the like in which a plurality of elongated leads are arranged in parallel and a longitudinal side surface of each lead is connected to an electrode by plating treatment with high quality. [Solution] An electrode connection structure in which a semiconductor chip 12 electrode and/or a substrate electrode is connected to a plurality of elongated leads 11 of a lead frame 10 by plating. The plurality of elongated leads 11 of the lead frame 10 are arranged in parallel, and a longitudinal side surface of each lead 11 is connected to the semiconductor chip 12 electrode and/or the substrate electrode by plating.
    Type: Application
    Filed: March 7, 2017
    Publication date: April 4, 2019
    Inventors: Kohei Tatsumi, Kazutoshi Ueda, Nobuaki Sato, Koji Shimizu
  • Patent number: 9960140
    Abstract: The present invention can give a joining structure using metal nanoparticles to join the same types or different types of metal where when one surface metal is Al based, the parts are joined through a joining layer containing Ni nanoparticles, whereby a good joining strength is obtained. Further, by using two joining layers (6, 8) including metal nanoparticles to sandwich metal foil (7) so as to form a joining layer and joining the same type or different types of surface metals (3-4) through this joining layer, it is possible to ease the thermal stress due to the difference in amounts of thermal expansion of joined members which have two surface metals.
    Type: Grant
    Filed: November 11, 2014
    Date of Patent: May 1, 2018
    Assignees: NIPPON STEEL & SUMITOMO METAL CORPORATION, WASEDA UNIVERSITY
    Inventors: Kohei Tatsumi, Shinji Ishikawa, Norie Matsubara, Masamoto Tanaka
  • Patent number: 9601448
    Abstract: An electrode connection structure includes: a first electrode of an electrical circuit; and a second electrode of the electrical circuit that is electrically connected to the first electrode. The first and second electrodes are oppositely disposed in direct or indirect contact with each other. A plated lamination is substantially uniformly formed by plating process from a surface of a contact region and opposed surfaces of the first and second electrodes. A void near the surface of the contact region is filled by formation of the plated lamination. Portions of the plated lamination formed from the opposed surfaces of the first and second electrodes in a region other than the contact region are not joined together.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: March 21, 2017
    Assignee: WASEDA UNIVERSITY
    Inventor: Kohei Tatsumi
  • Publication number: 20160240505
    Abstract: The present invention can give a joining structure using metal nanoparticles to join the same types or different types of metal where when one surface metal is Al based, the parts are joined through a joining layer containing Ni nanoparticles, whereby a good joining strength is obtained. Further, by using two joining layers (6, 8) including metal nanoparticles to sandwich metal foil (7) so as to form a joining layer and joining the same type or different types of surface metals (3-4) through this joining layer, it is possible to ease the thermal stress due to the difference in amounts of thermal expansion of joined members which have two surface metals.
    Type: Application
    Filed: November 11, 2014
    Publication date: August 18, 2016
    Applicants: NIPPON STEEL & SUMITOMO METAL CORPORATION, WASEDA University
    Inventors: Kohei TATSUMI, Shinji ISHIKAWA, Norie MATSUBARA, Masamoto TANAKA
  • Publication number: 20160225730
    Abstract: An electrode connection structure includes: a first electrode of an electrical circuit; and a second electrode of the electrical circuit that is electrically connected to the first electrode. The first and second electrodes are oppositely disposed in direct or indirect contact with each other. A plated lamination is substantially uniformly formed by plating process from a surface of a contact region and opposed surfaces of the first and second electrodes. A void near the surface of the contact region is filled by formation of the plated lamination. Portions of the plated lamination formed from the opposed surfaces of the first and second electrodes in a region other than the contact region are not joined together.
    Type: Application
    Filed: April 8, 2016
    Publication date: August 4, 2016
    Inventor: Kohei Tatsumi
  • Patent number: 9059003
    Abstract: It is an object of the present invention to provide a power semiconductor device, which is capable of being operable regardless of thermal stress generation, reducing a heat generation from wire, securing the reliability of bonding portion when the device is used for dealing with a large amount current and/or under a high temperature atmosphere, a method of manufacturing the device and a bonding wire. In a power semiconductor device in which a metal electrode (die electrode 3) on a power semiconductor die 2 and another metal electrode (connection electrode 4) are connected by metal wire 5 using wedge bonding connection, the metal wire is Ag or Ag alloy wire of which diameter is greater than 50 ?m and not greater than 2 mm and the die 3 has thereon one or more metal and/or alloy layers, each of the layer(s) being 50 ? or more in thickness and a metal for the layer is selected from Ni, Cr, Cu, Pd, V, Ti, Pt, Zn, Ag, Au, W and Al.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: June 16, 2015
    Assignees: NIPPON MICROMETAL CORPORATION, WASEDA UNIVERSITY
    Inventors: Kohei Tatsumi, Takashi Yamada, Daizo Oda
  • Publication number: 20140327018
    Abstract: It is an object of the present invention to provide a power semiconductor device, which is capable of being operable regardless of thermal stress generation, reducing a heat generation from wire, securing the reliability of bonding portion when the device is used for dealing with a large amount current and/or under a high temperature atmosphere, a method of manufacturing the device and a bonding wire. In a power semiconductor device in which a metal electrode (die electrode 3) on a power semiconductor die 2 and another metal electrode (connection electrode 4) are connected by metal wire 5 using wedge bonding connection, the metal wire is Ag or Ag alloy wire of which diameter is greater than 50 ?m and not greater than 2 mm and the die 3 has thereon one or more metal and/or alloy layers, each of the layer(s) being 50 ? or more in thickness and a metal for the layer is selected from Ni, Cr, Cu, Pd, V, Ti, Pt, Zn, Ag, Au, W and Al.
    Type: Application
    Filed: February 22, 2013
    Publication date: November 6, 2014
    Inventors: Kohei Tatsumi, Takashi Yamada, Daizo Oda
  • Patent number: 8104663
    Abstract: The periphery of a mask (3) is formed higher than a region where a ball holding hole (3a) is formed, a work (1) is arranged at a lower section of the ball holding hole (3a) of the mask (3), and the ball holding hole (3a) and an electrode of the work (1) are aligned with each other. A ball (B) is applied on the mask (3), and in such state, vibration is applied to the mask (3) to move the solder ball (B) on the surface of the mask (3) and drop the solder ball (B) into the ball holding hole (3a). The periphery of the mask (3) is permitted to be lower than the ball holding hole (3a), and an excessive portion of the solder ball (B) is recovered from over the mask (3).
    Type: Grant
    Filed: May 8, 2008
    Date of Patent: January 31, 2012
    Assignee: Nippon Steel Materials Co., Ltd.
    Inventors: Shinji Ishikawa, Eiji Hashino, Kohei Tatsumi
  • Patent number: 8097960
    Abstract: There is provided a bonding wire which does not cause a leaning failure or the like. A semiconductor mounting bonding wire has a breaking elongation of 7 to 20%, and stress at 1% elongation is greater than or equal to 90% of a tensile strength and is less than or equal to 100% thereof.
    Type: Grant
    Filed: June 26, 2008
    Date of Patent: January 17, 2012
    Assignees: Nippon Steel Materials Co., Ltd, Nippon Micrometal Corporation
    Inventors: Shinichi Terashima, Tomohiro Uno, Kohei Tatsumi, Takashi Yamada, Atsuo Ikeda, Daizo Oda
  • Publication number: 20110308371
    Abstract: There are provided a fixed-abrasive grain saw wire with a superior cutting performance and a manufacturing method thereof. Particularly, there are provided a fixed-abrasive grain saw wire with abrasive grains adhered to a metal wire via a Zn-based or Sn-based low-melting-point metal and a high-melting-point metal having a melting point higher than that of the low-melting-point metal, and a manufacturing method thereof.
    Type: Application
    Filed: December 18, 2009
    Publication date: December 22, 2011
    Applicant: NIPPON STEEL MATERIALS CO., LTD.
    Inventors: Mitsuru Morita, Hiroaki Sakamoto, Masamoto Tanaka, Kohei Tatsumi
  • Patent number: 8044408
    Abstract: The invention provides a high-quality SiC single-crystal substrate, a seed crystal for producing the high-quality SiC single-crystal substrate, and a method of producing the high-quality SiC single-crystal substrate, which enable improvement of device yield and stability. Provided is an SiC single-crystal substrate wherein, when the SiC single-crystal substrate is divided into 5-mm square regions, such regions in which dislocation pairs or dislocation rows having intervals between their dislocation end positions of 5 ?m or less are present among the dislocations that have ends at the substrate surface account for 50% or less of all such regions within the substrate surface and the dislocation density in the substrate of dislocations other than the dislocation pairs or dislocation is 8,000/cm2.
    Type: Grant
    Filed: May 20, 2009
    Date of Patent: October 25, 2011
    Assignee: Nippon Steel Corporation
    Inventors: Tatsuo Fujimoto, Kohei Tatsumi, Taizo Hoshino, Masakazu Katsuno, Noboru Ohtani, Masashi Nakabayashi, Hiroshi Tsuge, Housei Hirano, Hirokatsu Yashiro
  • Patent number: 7969021
    Abstract: A bonding wire for a semiconductor device has a core wire and a periphery comprising a conductive metal mainly composed of an element common to both and/or an alloy or alloys of said metal and, between the core wire and the periphery, a diffusion layer or an intermetallic compound layer composed of the elements constituting the core wire and the periphery and a bonding wire for a semiconductor device characterized by having a core wire comprising a first conductive metal or an alloy mainly composed of the first conductive metal, a periphery comprising a second conductive metal different from the first conductive metal of the core wire or an alloy mainly composed of the second conductive metal, and, between the core wire and the periphery, a diffusion layer or an intermetallic compound layer and a method of producing the same.
    Type: Grant
    Filed: September 18, 2001
    Date of Patent: June 28, 2011
    Assignee: Nippon Steel Corporation
    Inventors: Tomohiro Uno, Shinichi Terashima, Kohei Tatsumi