Abstract: A method for producing methanol allows the temperature of the catalyst layer to fall within an appropriate temperature range, reduces energy used, and achieves higher carbon yield. In a synthesis loop including at least two synthesis steps and two separation steps, a first mixed gas is obtained by mixing the final unreacted gas with a fraction of the make-up gas, methanol is synthesized from the first mixed gas after preheating, a first unreacted gas is separated from the obtained first reaction mixture, a final mixed gas is obtained by finally mixing the unreacted gas and a fraction of the make-up gas, the final mixed gas after preheating is further increased in pressure and then methanol is synthesized, a final unreacted gas is separated from the obtained final reaction mixture, and the reaction temperature of the catalyst layer is controlled by the indirect heat exchange with pressurized boiling water.

Abstract: A method for producing methanol allows the temperature of the catalyst layer to fall within an appropriate temperature range, reduces energy used, and achieves higher carbon yield. In a synthesis loop including at least two synthesis steps and two separation steps, a first mixed gas is obtained by mixing the final unreacted gas with a fraction of the make-up gas, methanol is synthesized from the first mixed gas after preheating, a first unreacted gas is separated from the obtained first reaction mixture, a final mixed gas is obtained by finally mixing the unreacted gas and a fraction of the make-up gas, the final mixed gas after preheating is further increased in pressure and then methanol is synthesized, a final unreacted gas is separated from the obtained final reaction mixture, and the reaction temperature of the catalyst layer is controlled by the indirect heat exchange with pressurized boiling water.

Abstract: Synthesizing methanol from a synthesis gas and separating an unreacted gas from a reaction mixture obtained by passing through the synthesis step, the method including a synthesis loop having at least two synthesis steps and at least two separation steps; obtaining a first mixed gas by increasing through a circulator a pressure of a residual gas, obtained by removing a purge gas from the final unreacted gas separated from the final reaction mixture subsequent to the final synthesis step, and by mixing the residual gas with a fraction of a make-up gas; synthesizing methanol; separating a first unreacted gas from the first reaction mixture obtained in the synthesizing step; obtaining a second mixed gas by mixing the first unreacted gas and a fraction of the make-up gas; finally synthesizing methanol; and separating the final unreacted gas from the final reaction mixture obtained in the final synthesis step.

Abstract: Synthesizing methanol from a synthesis gas and separating an unreacted gas from a reaction mixture obtained by passing through the synthesis step, the method including a synthesis loop having at least two synthesis steps and at least two separation steps; obtaining a first mixed gas by increasing through a circulator a pressure of a residual gas, obtained by removing a purge gas from the final unreacted gas separated from the final reaction mixture subsequent to the final synthesis step, and by mixing the residual gas with a fraction of a make-up gas; synthesizing methanol; separating a first unreacted gas from the first reaction mixture obtained in the synthesizing step; obtaining a second mixed gas by mixing the first unreacted gas and a fraction of the make-up gas; finally synthesizing methanol; and separating the final unreacted gas from the final reaction mixture obtained in the final synthesis step.

Abstract: A power control system for a network system in which a plurality of devices are connected over a network can adequately distribute limited power according to the operational state of each device while keeping a high reliability. A device operating in normal mode broadcasts a power accommodation request when the power of the device is insufficient. Upon reception of the power accommodation request, devices operating in low-power mode send accommodatable power values to the requesting device, and sends a low-power mode fixation notification indicating that operational mode is fixed to the low-power mode to a controller. Upon reception of the low-power mode fixation notification from the notifying devices, the controller sets a job assignment ratio to the notifying devices lower than that of the requesting device.

Abstract: A layout apparatus stores a plurality of capacitor cells which are classifiable into a first classification for identifying capacitor cells having different sizes by frequency characteristic correlating with gate width of a capacitor and a second classification for identifying capacitor cells having different frequency characteristics by cell size.

Abstract: An apparatus includes a first selector which selects a test data during a first operation mode, and selects a first input data during a second operation mode, a first latch circuit which latches an output signal of the first selector according to a first clock signal, a second selector which selects one from a second input data and an output signal of the first latch circuit, and a second latch circuit which latches the second input data sent from the second selector according to a second clock signal during the second operation mode, and passes through the output signal of the first latch circuit sent from the second selector during the first operation mode.

Abstract: An element placement system including a placement and routing library that stores element information about logical elements to be placed, placement information containing region information of regions in which logical elements can be placed, and routing information necessary to execute routing, a placement improvement library that stores specified element information about specified logical elements being logical elements specified to place capacitors in the vicinity thereof, a placement unit that places logical elements according to input data containing connection data between logical elements and the placement information stored in the placement and routing library, a placement improvement unit that improves a result of placement by the placement unit by moving logical elements other than specified logical elements stored in the placement improvement library to collect spaces into the vicinity of the specified logical elements, a routing unit that routes logical elements after placement improvement by the

Abstract: An apparatus, including: a circuit which operates according to a clock signal, the circuit operating with a delay, and a clock generator which generates the clock signal with a duty ratio, the duty ratio being adapted to the delay.

Abstract: An integrated circuit with a scan testing circuit which enables reducing power consumption in normal operation mode is provided. A power-supply controller applies a power-supply voltage to internal and external transmission circuits in scan test mode and stops applying the power supply voltage in normal operation mode. Thus, power consumption associated with operations of the internal and external transmission circuits is eliminated, thereby reducing power consumption in normal operation mode.

Abstract: A layout apparatus stores a plurality of capacitor cells which are classifiable into a first classification for identifying capacitor cells having different sizes by frequency characteristic correlating with gate width of a capacitor and a second classification for identifying capacitor cells having different frequency characteristics by cell size.

Abstract: An apparatus includes a first selector which selects a test data during a first operation mode, and selects a first input data during a second operation mode, a first latch circuit which latches an output signal of the first selector according to a first clock signal, a second selector which selects one from a second input data and an output signal of the first latch circuit, and a second latch circuit which latches the second input data sent from the second selector according to a second clock signal during the second operation mode, and passes through the output signal of the first latch circuit sent from the second selector during the first operation mode.

Abstract: A power control system for a network system in which a plurality of devices are connected over a network can adequately distribute limited power according to the operational state of each device while keeping a high reliability. A device operating in normal mode broadcasts a power accommodation request when the power of the device is insufficient. Upon reception of the power accommodation request, devices operating in low-power mode send accommodatable power values to the requesting device, and sends a low-power mode fixation notification indicating that operational mode is fixed to the low-power mode to a controller. Upon reception of the low-power mode fixation notification from the notifying devices, the controller sets a job assignment ratio to the notifying devices lower than that of the requesting device.

Abstract: An apparatus, including: a circuit which operates according to a clock signal, the circuit operating with a delay, and a clock generator which generates the clock signal with a duty ratio, the duty ratio being adapted to the delay.

Abstract: A method of designing a layout of a functional block and an on-chip capacitor in a semiconductor integrated circuit, includes the steps of (a) designing a layout of a capacitor/block including a functional block, and an on-chip capacitor having a predetermined capacity and disposed adjacent to the functional block, (b) judging whether the layout resulted from the step (a) satisfies predetermined requirements, (c) designing again a layout of a capacitor/block including an on-chip capacitor having a capacity smaller than a capacity of an on-chip capacitor of the previously designed capacitor/block, only when the layout resulted from the step (a) is judged not to satisfy the predetermined requirements, and (d) judging whether the layout resulted from the step (c) satisfies the predetermined requirements. The steps (c) and (d) are repeatedly carried out until the layout satisfies the predetermined requirements.

Abstract: A method of designing a layout of functional blocks and on-chip capacitors in a semiconductor integrated circuit, includes the steps of, in sequence, (a) placing a functional block, (b) placing an on-chip capacitor in an area which remains vacant after the step (a) has been carried out, (c) overlapping a portion of the functional block having been placed in the step (a) and a portion of the on-chip capacitor having been placed in the step (b) each other, if possible, and (d) placing an on-chip capacitor in a vacant area caused by carrying out the step (c).

Abstract: An element placement system including a placement and routing library that stores element information about logical elements to be placed, placement information containing region information of regions in which logical elements can be placed, and routing information necessary to execute routing, a placement improvement library that stores specified element information about specified logical elements being logical elements specified to place capacitors in the vicinity thereof, a placement unit that places logical elements according to input data containing connection data between logical elements and the placement information stored in the placement and routing library, a placement improvement unit that improves a result of placement by the placement unit by moving logical elements other than specified logical elements stored in the placement improvement library to collect spaces into the vicinity of the specified logical elements, a routing unit that routes logical elements after placement improvement by the

Abstract: An element placement system including a placement and routing library that stores element information about logical elements to be placed, placement information containing region information of regions in which logical elements can be placed, and routing information necessary to execute routing, a placement improvement library that stores specified element information about specified logical elements being logical elements specified to place capacitors in the vicinity thereof, a placement unit that places logical elements according to input data containing connection data between logical elements and the placement information stored in the placement and routing library, a placement improvement unit that improves a result of placement by the placement unit by moving logical elements other than specified logical elements stored in the placement improvement library to collect spaces into the vicinity of the specified logical elements, a routing unit that routes logical elements after placement improvement by the

Abstract: An integrated circuit with a scan testing circuit which enables reducing power consumption in normal operation mode is provided. A power-supply controller applies a power-supply voltage to internal and external transmission circuits in scan test mode and stops applying the power supply voltage in normal operation mode. Thus, power consumption associated with operations of the internal and external transmission circuits is eliminated, thereby reducing power consumption in normal operation mode.

Abstract: A method of designing a layout of functional blocks and on-chip capacitors in a semiconductor integrated circuit, includes the steps of, in sequence, (a) placing a functional block, (b) placing an on-chip capacitor in an area which remains vacant after the step (a) has been carried out, (c) overlapping a portion of the functional block having been placed in the step (a) and a portion of the on-chip capacitor having been placed in the step (b) each other, if possible, and (d) placing an on-chip capacitor in a vacant area caused by carrying out the step (c).