Patents by Inventor Kohei WAKAHARA

Kohei WAKAHARA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9898068
    Abstract: A semiconductor device includes a CPU core, a frequency regulating circuit, and a frequency control circuit. The frequency regulating circuit includes a table. The frequency control circuit provides a clock to the CPU core. The CPU core outputs an operating state signal indicating an operating state of the CPU core. The frequency regulating circuit controls a frequency of the clock based on the table and the operating state signal. Thus it is possible to provide a semiconductor device that allows performance to follow a dynamically changing load.
    Type: Grant
    Filed: January 19, 2014
    Date of Patent: February 20, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Go Sado, Masaki Fujigaya, Kohei Wakahara, Keiji Hasegawa
  • Patent number: 9195260
    Abstract: A semiconductor device 1 includes a clock generation circuit 15 that changes a frequency of an output clock signal according to a control signal div, an arithmetic circuit (e.g., CPU0) that operates according to the clock signal, a storage circuit (e.g., IC0) that is activated according to access from the arithmetic circuit CPU0, a memory access detection unit 12 that detects a number of accesses from the arithmetic circuit CPU0 to the storage circuit IC0, and when the number of accesses increases, outputs a request signal (e.g., psreq1), and a clock control circuit 14 that generates the control signal div for lowering the frequency of the clock signal according to the request signal psreq1.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: November 24, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Tsugio Matsuyama, Kohei Wakahara, Masaki Fujigaya, Takahiro Irita
  • Publication number: 20150116010
    Abstract: A semiconductor device 1 includes a clock generation circuit 15 that changes a frequency of an output clock signal according to a control signal div, an arithmetic circuit (e.g., CPU0) that operates according to the clock signal, a storage circuit (e.g., IC0) that is activated according to access from the arithmetic circuit CPU0, a memory access detection unit 12 that detects a number of accesses from the arithmetic circuit CPU0 to the storage circuit IC0, and when the number of accesses increases, outputs a request signal (e.g., psreq1), and a clock control circuit 14 that generates the control signal div for lowering the frequency of the clock signal according to the request signal psreq1.
    Type: Application
    Filed: December 22, 2014
    Publication date: April 30, 2015
    Inventors: Tsugio Matsuyama, Kohei Wakahara, Masaki Fujigaya, Takahiro Irita
  • Patent number: 8935553
    Abstract: A semiconductor device 1 includes a clock generation circuit 15 that changes a frequency of an output clock signal according to a control signal div, an arithmetic circuit (e.g., CPU0) that operates according to the clock signal, a storage circuit (e.g., IC0) that is activated according to access from the arithmetic circuit CPU0, a memory access detection unit 12 that detects a number of accesses from the arithmetic circuit CPU0 to the storage circuit IC0, and when the number of accesses increases, outputs a request signal (e.g., psreq1), and a clock control circuit 14 that generates the control signal div for lowering the frequency of the clock signal according to the request signal psreq1.
    Type: Grant
    Filed: July 4, 2012
    Date of Patent: January 13, 2015
    Assignee: Renesas Mobile Corporation
    Inventors: Tsugio Matsuyama, Kohei Wakahara, Masaki Fujigaya, Takahiro Irita
  • Publication number: 20140215243
    Abstract: A semiconductor device includes a CPU core, a frequency regulating circuit, and a frequency control circuit. The frequency regulating circuit includes a table. The frequency control circuit provides a clock to the CPU core. The CPU core outputs an operating state signal indicating an operating state of the CPU core. The frequency regulating circuit controls a frequency of the clock based on the table and the operating state signal. Thus it is possible to provide a seiconductor device that allows performance to follow a dynamically changing load.
    Type: Application
    Filed: January 19, 2014
    Publication date: July 31, 2014
    Applicant: Renesas Mobile Corporation
    Inventors: Go Sado, Masaki Fujigaya, Kohei Wakahara, Keiji Hasegawa
  • Publication number: 20130009687
    Abstract: A semiconductor device 1 includes a clock generation circuit 15 that changes a frequency of an output clock signal according to a control signal div, an arithmetic circuit (e.g., CPU0) that operates according to the clock signal, a storage circuit (e.g., IC0) that is activated according to access from the arithmetic circuit CPU0, a memory access detection unit 12 that detects a number of accesses from the arithmetic circuit CPU0 to the storage circuit IC0, and when the number of accesses increases, outputs a request signal (e.g., psreq1), and a clock control circuit 14 that generates the control signal div for lowering the frequency of the clock signal according to the request signal psreq1.
    Type: Application
    Filed: July 4, 2012
    Publication date: January 10, 2013
    Inventors: Tsugio MATSUYAMA, Kohei WAKAHARA, Masaki FUJIGAYA, Takahiro IRITA