Patents by Inventor Kohei YAMAUCHI

Kohei YAMAUCHI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240136325
    Abstract: A circuit board having a circuit pattern on a base plate and an additional metal layer laid and bonded on the circuit pattern, wherein the additional metal layer comprises an attachment plane portion configured to fix a semiconductor chip using solder, and an engagement uneven portion provided adjacent to the attachment plane portion, wherein the attachment plane portion is a face having unevenness smaller than the engagement uneven portion.
    Type: Application
    Filed: January 27, 2022
    Publication date: April 25, 2024
    Inventors: Ryo TANAKA, Yuichiro YAMAUCHI, Kohei SUZUKI
  • Publication number: 20230407547
    Abstract: A filter member is detachably mounted in a filter case formed with an inflow port through which washing water flows in and an outflow port through which the washing water flows out. The filter member includes a rib-shaped portion partitioning through holes adjacent to each other. At least one of the through holes is inclined from an inner peripheral surface of the filter member.
    Type: Application
    Filed: June 5, 2023
    Publication date: December 21, 2023
    Inventors: MASARU MISUMI, YUI KUMON, KOHEI YAMAUCHI
  • Patent number: 11624562
    Abstract: A heat sink includes a base plate; a cover overlapping the base plate; fins, each having a plate-like shape projecting from the base plate in a direction perpendicular to the base plate, located between the base plate and the cover; one or a plurality of first fin groups composed of a plurality of the fins arranged with a gap therebetween in a first direction; and one or a plurality of second fin groups composed of a plurality of the fins arranged with a gap therebetween in the first direction, and adjacent to the first fin group with a gap therebetween in a second direction. Positions in the first direction of the fins belonging to the second fin group are displaced with respect to positions in the first direction of the fins belonging to the first fin group. Each of the fines has an S-shape.
    Type: Grant
    Filed: August 29, 2022
    Date of Patent: April 11, 2023
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takumi Nakamura, Eiji Anzai, Tomoyuki Hirayama, Yutaka Hirano, Ryoichi Kato, Hiromichi Gohara, Kohei Yamauchi
  • Patent number: 11581252
    Abstract: A semiconductor module includes at least two semiconductor elements connected in parallel; a control circuit board placed between the at least two semiconductor elements; a control terminal for external connection; a first wiring member that connects the control terminal and the control circuit board; and a second wiring member that connects a control electrode of one of the at least two semiconductor elements and the control circuit board, wherein the second wiring member is wire-bonded from the control electrode towards the control circuit board, and has a first end on the control electrode and a second end on the control circuit board, the first end having a cut end face facing upward normal to a surface of the control electrode and the second end having a cut end face facing sideways parallel to a surface of the control circuit board.
    Type: Grant
    Filed: March 1, 2021
    Date of Patent: February 14, 2023
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takafumi Yamada, Kohei Yamauchi, Tatsuhiko Asai, Hiromichi Gohara
  • Patent number: 11556069
    Abstract: Toner includes, as toner particles, first particles and second particles. The first particles each include a first core and a first shell layer covering a surface of the first core. The first core contains a first binder resin and is free from metal stearates. The second particles each include a second core and a second shell layer covering a surface of the second core. The second core contains a metal stearate. The first shell layer and the second shell layer are formed of resins of the same type, respectively. The content of the metal stearate in the second core is 50% by mass or more with respect to the mass of the second core as a whole. The number ratio of the second particles is 5% or more but 25% or less of the total number of the first particles and the second particles.
    Type: Grant
    Filed: October 22, 2020
    Date of Patent: January 17, 2023
    Assignee: KYOCERA DOCUMENT SOLUTIONS INC.
    Inventor: Kohei Yamauchi
  • Publication number: 20220412670
    Abstract: A heat sink includes a base plate; a cover overlapping the base plate; fins, each having a plate-like shape projecting from the base plate in a direction perpendicular to the base plate, located between the base plate and the cover; one or a plurality of first fin groups composed of a plurality of the fins arranged with a gap therebetween in a first direction; and one or a plurality of second fin groups composed of a plurality of the fins arranged with a gap therebetween in the first direction, and adjacent to the first fin group with a gap therebetween in a second direction. Positions in the first direction of the fins belonging to the second fin group are displaced with respect to positions in the first direction of the fins belonging to the first fin group. Each of the fines has an S-shape.
    Type: Application
    Filed: August 29, 2022
    Publication date: December 29, 2022
    Inventors: Takumi NAKAMURA, Eiji ANZAI, Tomoyuki HIRAYAMA, Yutaka HIRANO, Ryoichi KATO, Hiromichi GOHARA, Kohei YAMAUCHI
  • Patent number: 11380599
    Abstract: There is provided a semiconductor module including: a base for semiconductor cooling; a stacked substrate provided above the base; a semiconductor chip provided above the stacked substrate; a coating layer provided on an upper surface of the semiconductor chip; and a sealing resin for sealing the semiconductor chip, in which the base is in contact with the sealing resin.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: July 5, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Kohei Yamauchi, Tatsuhiko Asai
  • Publication number: 20220160007
    Abstract: The present invention addresses the problem of obtaining a magnesium chloride-containing powdered seasoning with suppressed deliquescence that is storable for a long time. The present inventors have found that by coating magnesium chloride with a certain amount or more of starch, deliquescence of magnesium chloride is suppressed, and the seasoning can be stored in powder form for a long time. Moreover, they have found that by using oxidized starch as the starch, a powdered seasoning that can be utilized in a wider range of application without affecting viscosity or a taste of powdered soup is obtained. Owing to the completion of the present invention, a magnesium chloride-containing powdered seasoning with suppressed deliquescence that is storable for a long time can be obtained.
    Type: Application
    Filed: August 17, 2020
    Publication date: May 26, 2022
    Inventors: Taiga NAKATANI, Norie OGUCHI, Kohei YAMAUCHI, Hiroyuki KONO, Shinji TAMAKI
  • Patent number: 11201121
    Abstract: A semiconductor device encompasses a cooler made of ceramics, having a first main face and a second main face, being parallel and opposite to the first main face, defined by two opposite side faces perpendicular to the first and second main faces, a plurality of conductive-pattern layers delineated on the first main face, a semiconductor chip mounted on the first main face via one of the plurality of conductive-pattern layers, and a seal member configured to seal the semiconductor chip.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: December 14, 2021
    Assignee: FUJI ELECTRIC CO., LTD
    Inventors: Kohei Yamauchi, Hiromichi Gohara, Ryoichi Kato, Yoshinari Ikeda, Katsumi Taniguchi
  • Publication number: 20210287978
    Abstract: A semiconductor module includes at least two semiconductor elements connected in parallel; a control circuit board placed between the at least two semiconductor elements; a control terminal for external connection; a first wiring member that connects the control terminal and the control circuit board; and a second wiring member that connects a control electrode of one of the at least two semiconductor elements and the control circuit board, wherein the second wiring member is wire-bonded from the control electrode towards the control circuit board, and has a first end on the control electrode and a second end on the control circuit board, the first end having a cut end face facing upward normal to a surface of the control electrode and the second end having a cut end face facing sideways parallel to a surface of the control circuit board.
    Type: Application
    Filed: March 1, 2021
    Publication date: September 16, 2021
    Applicant: Fuji Electric Co., Ltd.
    Inventors: Takafumi YAMADA, Kohei YAMAUCHI, Tatsuhiko ASAI, Hiromichi GOHARA
  • Publication number: 20210124282
    Abstract: Toner includes, as toner particles, first particles and second particles. The first particles each include a first core and a first shell layer covering a surface of the first core. The first core contains a first binder resin and is free from metal stearates. The second particles each include a second core and a second shell layer covering a surface of the second core. The second core contains a metal stearate. The first shell layer and the second shell layer are formed of resins of the same type, respectively. The content of the metal stearate in the second core is 50% by mass or more with respect to the mass of the second core as a whole. The number ratio of the second particles is 5% or more but 25% or less of the total number of the first particles and the second particles.
    Type: Application
    Filed: October 22, 2020
    Publication date: April 29, 2021
    Inventor: Kohei YAMAUCHI
  • Publication number: 20210102760
    Abstract: A heat sink includes: a base plate; a cover overlapping the base plate; a fin having a plate-like shape projecting from the base plate, the fin being located between the base plate and the cover; a first fin group composed of a plurality of the fins arranged with a gap therebetween in a first direction parallel to the base plate; and a second fin group composed of a plurality of the fins arranged with a gap therebetween in the first direction, and adjacent to the first fin group with a gap therebetween in a second direction parallel to an inflow direction of refrigerant. A longitudinal direction of the fin is along the second direction. A position in the first direction of the fin of the second fin group is displaced with respect to a position in the first direction of the fin of the first fin group.
    Type: Application
    Filed: December 16, 2020
    Publication date: April 8, 2021
    Inventors: Takumi NAKAMURA, Eiji ANZAI, Tomoyuki HIRAYAMA, Yutaka HIRANO, Ryoichi KATO, Hiromichi GOHARA, Kohei YAMAUCHI
  • Patent number: 10971431
    Abstract: A semiconductor device includes: a first cooling device including a plurality of first flow channels through which a fluid flows, between a first main surface and a second main surface opposed to each other; a second cooling device including a plurality of second flow channels through which a fluid flows, between a third main surface and a fourth main surface parallel to the first main surface; a semiconductor element interposed between the first main surface and the third main surface facing each other; and a control terminal penetrating from the third main surface to the fourth main surface in a terminal-penetrating region defined at a predetermined position between the plurality of second flow channels, and electrically connected to a control electrode of the semiconductor element.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: April 6, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Kohei Yamauchi, Hiromichi Gohara, Katsumi Taniguchi
  • Patent number: 10916491
    Abstract: A semiconductor module includes a semiconductor element having one and the other surface, a lead terminal connected electrically and thermally to the semiconductor element, a first solder which bonds the lead terminal and the one surface of the semiconductor element together, a circuit layer over which the semiconductor element is disposed and a second solder which bonds the other surface of the semiconductor element and the circuit layer together. The inequality (A/B)<1 holds, where A and B are the tensile strength of the first and second solder, respectively. As a result, even if the lead terminal which thermally expands because of heat generated by the semiconductor element expands or contracts toward the semiconductor element, a stress applied by the lead terminal is absorbed and relaxed by the first solder. This prevents damage to the surface electrode of the semiconductor element by suppressing the occurrence of cracks.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: February 9, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Ryoichi Kato, Kohei Yamauchi, Hiromichi Gohara, Tatsuhiko Asai
  • Publication number: 20200402880
    Abstract: There is provided a semiconductor module including: a base for semiconductor cooling; a stacked substrate provided above the base; a semiconductor chip provided above the stacked substrate; a coating layer provided on an upper surface of the semiconductor chip; and a sealing resin for sealing the semiconductor chip, in which the base is in contact with the sealing resin.
    Type: Application
    Filed: February 24, 2020
    Publication date: December 24, 2020
    Inventors: Kohei YAMAUCHI, Tatsuhiko ASAI
  • Publication number: 20190371705
    Abstract: A semiconductor device includes: a first cooling device including a plurality of first flow channels through which a fluid flows, between a first main surface and a second main surface opposed to each other; a second cooling device including a plurality of second flow channels through which a fluid flows, between a third main surface and a fourth main surface parallel to the first main surface; a semiconductor element interposed between the first main surface and the third main surface facing each other; and a control terminal penetrating from the third main surface to the fourth main surface in a terminal-penetrating region defined at a predetermined position between the plurality of second flow channels, and electrically connected to a control electrode of the semiconductor element.
    Type: Application
    Filed: March 22, 2019
    Publication date: December 5, 2019
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Kohei YAMAUCHI, Hiromichi Gohara, Katsumi Taniguchi
  • Patent number: 10446460
    Abstract: The semiconductor device includes a first insulating circuit substrate; a semiconductor chip including a plurality of control electrodes, disposed on the first insulating circuit substrate; a second insulating circuit substrate including a plurality of first through-holes in which conductive members are arranged on inner walls and/or an outer periphery of ends of the first through-holes, the second insulating circuit substrate being disposed above the semiconductor chips; and first pins inserted into the first through-holes and having at one end a columnar part connected to the control electrodes of the semiconductor chips, and having at another end a head part that is wider than an inner diameter of the first through-holes.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: October 15, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Hiromichi Gohara, Kohei Yamauchi, Shinji Tada, Tatsuo Nishizawa, Yoshitaka Nishimura
  • Patent number: 10394147
    Abstract: Toner particles of a toner contain a non-crystalline polyester resin, a crystalline polyester resin, a styrene-acrylic acid-based resin, and an ester wax. The crystalline polyester resin has a repeating unit derived from an acrylic acid-based monomer and a repeating unit derived from a styrene-based monomer. The styrene-acrylic acid-based resin has a repeating unit derived from an acrylic acid-based monomer having an amino group and a repeating unit derived from a styrene-based monomer. An amino group ratio in the styrene-acrylic acid-based resin is at least 40% and no greater than 60%. The toner has a storage elastic modulus of at least 1.00×105 Pa and no greater than 5.00×105 Pa at 90° C. The ester wax has a melting point of at least 60° C. and no higher than 80° C. A dispersion diameter of the ester wax in the toner particles is at least 500 nm and no greater than 1,000 nm.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: August 27, 2019
    Assignee: KYOCERA Document Solutions Inc.
    Inventors: Kohei Yamauchi, Toshiki Takemori
  • Patent number: 10365571
    Abstract: An electrostatic latent image developing toner includes a plurality of toner particles containing a non-crystalline polyester resin and a crystalline polyester resin. The toner particles contain as the crystalline polyester resin a dispersoid of crystallized crystalline polyester resin (CPES) domains. The CPES domains of the CPES dispersoid have an aspect ratio of at least 3.40 and no greater than 10.0 in terms of number average value. The toner particles have a roundness of at least 0.950 and no greater than 0.970 in terms of number average value. In a cross-sectional image of each of the toner particles, a ratio of a total area occupied by the CPES dispersoid to a cross-sectional area of the toner particle is at least 10.0% and no greater than 30.0%. The non-crystalline polyester resin includes a repeating unit derived from alkenyl succinic anhydride. The crystalline polyester resin includes a repeating unit derived from n-butyl methacrylate.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: July 30, 2019
    Assignee: KYOCERA Document Solutions Inc.
    Inventors: Toshiki Takemori, Kohei Yamauchi
  • Patent number: 10332845
    Abstract: A semiconductor device includes: an upper-surface electrode on an upper surface of a semiconductor element; a plated layer on an upper surface of the upper-surface electrode; gate runners penetrating the plated layer and formed to extend above the upper surface of the semiconductor element; and a metal connecting plate arranged above the plated layer and electrically connected to the upper-surface electrode, wherein the metal connecting plate has a joint portion parallel to the upper surface of the semiconductor element and has a rising portion at an end of the joint portion, the rising portion extending in a direction away from the semiconductor element, and in a plane parallel to the upper surface of the semiconductor element, a first distance, which is a shortest distance between the rising portion and the gate runner not intersecting the rising portion, is equal to or longer than 1 mm.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: June 25, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takafumi Yamada, Hiromichi Gohara, Ryoichi Kato, Kohei Yamauchi